ADC12D1000RF, ADC12D1600RF ADC12D1600/1000RF 12-Bit, 3.2/2.0 GSPS RF Sampling ADC Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
ADC12D1000RF, ADC12D1600RF www.ti.com SNAS519G – JULY 2011 – REVISED APRIL 2013 ADC12D1600/1000RF 12-Bit, 3.2/2.0 GSPS RF Sampling ADC Check for Samples: ADC12D1000RF, ADC12D1600RF 1 Introduction 1.1 Features 12 • Excellent Noise and Linearity up to and Above fIN = 2.7 GHz • Configurable to Either 3.2/2.
ADC12D1000RF, ADC12D1600RF www.ti.com 1.3 SNAS519G – JULY 2011 – REVISED APRIL 2013 Description The 12-bit 3.2/2.0 GSPS ADC12D1600/1000RF is an RF-sampling GSPS ADC that can directly sample input frequencies up to and above 2.7 GHz.
ADC12D1000RF, ADC12D1600RF SNAS519G – JULY 2011 – REVISED APRIL 2013 2 Device Information 2.1 Block Diagram 2.2 RF Performance www.ti.com -40 -7 dBFS -10 dBFS -13 dBFS -16 dBFS IMD3(dBFS) -50 -60 -70 -80 -90 -100 0 1 2 3 FREQUENCY (GHz) 4 Figure 2-1.
ADC12D1000RF, ADC12D1600RF www.ti.com 2.
ADC12D1000RF, ADC12D1600RF SNAS519G – JULY 2011 – REVISED APRIL 2013 2.4 www.ti.com Ball Descriptions and Equivalent Circuits Table 2-1. Analog Front-End and Clock Balls Ball No. Name Equivalent Circuit Description Differential signal I- and Q-inputs. In the Non-Dual Edge Sampling (Non-DES) Mode, each I- and Qinput is sampled and converted by its respective channel with each positive transition of the CLK input. In Non-ECM (Non-Extended Control Mode) and DES Mode, both channels sample the I-input.
ADC12D1000RF, ADC12D1600RF www.ti.com SNAS519G – JULY 2011 – REVISED APRIL 2013 Table 2-1. Analog Front-End and Clock Balls (continued) Ball No. Name Equivalent Circuit Description VA VCMO C2 200k VCMO Enable AC Coupling 8 pF GND Bandgap Voltage Output or LVDS Common-mode Voltage Select. This pin provides a buffered version of the bandgap output voltage and is capable of sourcing/sinking 100 uA and driving a load of up to 80 pF.
ADC12D1000RF, ADC12D1600RF SNAS519G – JULY 2011 – REVISED APRIL 2013 www.ti.com Table 2-1. Analog Front-End and Clock Balls (continued) Ball No. Name Equivalent Circuit Description VA Y4/W5 50k AGND RCLK+/- 100 VA VBIAS 50k Reference Clock Input. When the AutoSync feature is active, and the ADC12D1600/1000RF is in Slave Mode, the internal divided clocks are synchronized with respect to this input clock. The delay on this clock may be adjusted when synchronizing multiple ADCs.
ADC12D1000RF, ADC12D1600RF www.ti.com SNAS519G – JULY 2011 – REVISED APRIL 2013 Table 2-2. Control and Status Balls (continued) Ball No. Name Equivalent Circuit VA D6 CAL GND Description Calibration cycle initiate. The user can command the device to execute a self-calibration cycle by holding this input high a minimum of tCAL_H after having held it low a minimum of tCAL_L.
ADC12D1000RF, ADC12D1600RF SNAS519G – JULY 2011 – REVISED APRIL 2013 www.ti.com Table 2-2. Control and Status Balls (continued) Ball No. Name Equivalent Circuit VA Y3 FSR GND VA W4 DDRPh GND Description Full-Scale input Range select. In Non-ECM, when this input is set to logic-low or logic-high, the fullscale differential input range for both I- and Qchannel inputs is set to the lower or higher FSR value, respectively.
ADC12D1000RF, ADC12D1600RF www.ti.com SNAS519G – JULY 2011 – REVISED APRIL 2013 Table 2-2. Control and Status Balls (continued) Ball No. Name Equivalent Circuit Description VA 100 k: B4 Serial Data-In. In ECM, serial data is shifted into the device on this pin while SCS signal is asserted (logic-low). SDI GND VA A3 Serial Data-Out. In ECM, serial data is shifted out of the device on this pin while SCS signal is asserted (logic-low). This output is tri-stated when SCS is de-asserted.
ADC12D1000RF, ADC12D1600RF SNAS519G – JULY 2011 – REVISED APRIL 2013 www.ti.com Table 2-3. Power and Ground Balls (continued) Ball No. Name Equivalent Circuit A1, A7, B2, B7, D4, D5, E4, K1, L1, T4, U4, U5, W2, W7, Y1, Y7, H8:N13 Description GND NONE Ground Return for the Analog circuitry. F2, G2, H3, J2, K4, L4, M2, N3, P2, R2, T2, T3, U1 GNDTC NONE Ground Return for the Track-and-Hold and Clock circuitry.
ADC12D1000RF, ADC12D1600RF www.ti.com SNAS519G – JULY 2011 – REVISED APRIL 2013 Table 2-4. High-Speed Digital Outputs (continued) Ball No.
ADC12D1000RF, ADC12D1600RF SNAS519G – JULY 2011 – REVISED APRIL 2013 3 Electrical Specifications 3.1 Absolute Maximum Ratings (1) (2) www.ti.com Supply Voltage (VA, VTC, VDR, VE) 2.2V Supply Difference max(VA/TC/DR/E)- min(VA/TC/DR/E) 0V to 100 mV −0.15V to (VA + 0.15V) Voltage on Any Input Pin (except VIN+/-) VIN+/- Voltage Range -0.5V to 2.
ADC12D1000RF, ADC12D1600RF www.ti.com SNAS519G – JULY 2011 – REVISED APRIL 2013 Operating Ratings(1)(2) (continued) Common Mode Input Voltage 3.3 VCMO - 150 mV < VCMI < VCMO +150 mV Package Thermal Resistance Package θJA θJC1 θJC2 292-Ball BGA Thermally Enhanced Package 16°C/W 2.9°C/W 2.5°C/W Soldering process must comply with Reflow Temperature Profile specifications. Refer to www.ti.com/packaging (1) (1) Reflow temperature profiles are different for lead-free and non-lead-free packages. 3.
ADC12D1000RF, ADC12D1600RF SNAS519G – JULY 2011 – REVISED APRIL 2013 3.5 www.ti.com Converter Electrical Characteristics Dynamic Converter Characteristics (1) Symbol Parameter Conditions Bandwidth ADC12D1600RF Typ Lim ADC12D1000RF Typ Lim Units (Limits) DESIQ Mode -3dB (2) 1.75 1.75 GHz -6dB 2.7 2.7 GHz -3dB (2) 1.2 1.2 GHz -6dB 2.3 2.3 GHz -9dB 2.7 2.7 GHz -12dB 3.0 3.0 GHz -3dB (2) 2.7 2.7 GHz -6dB 3.1 3.1 GHz -9dB 3.5 3.5 GHz -12dB 4.0 4.0 GHz D.C.
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ADC12D1000RF, ADC12D1600RF SNAS519G – JULY 2011 – REVISED APRIL 2013 3.7 Converter Electrical Characteristics I-Channel to Q-Channel Characteristics Symbol X-TALK (1) www.ti.com Parameter Conditions (1) Typ Lim ADC12D1000RF Typ Lim Units (Limits) Offset Match See 2 2 LSB Positive Full-Scale Match Zero offset selected in Control Register 2 2 LSB Negative Full-Scale Match Zero offset selected in Control Register 2 2 LSB Phase Matching (I, Q) fIN = 1.
ADC12D1000RF, ADC12D1600RF www.ti.com SNAS519G – JULY 2011 – REVISED APRIL 2013 3.10 Converter Electrical Characteristics Digital Control and Output Pin Characteristics Symbol Parameter Conditions ADC12D1600RF Typ Lim ADC12D1000RF Typ Lim Units (Limits) Digital Control Pins (DES, CalDly, CAL, PDI, PDQ, TPM, NDM, FSR, DDRPh, ECE, SCLK, SDI, SCS) VIH Logic High Input Voltage 0.7×VA 0.7×VA V (min) VIL Logic Low Input Voltage 0.3×VA 0.
ADC12D1000RF, ADC12D1600RF SNAS519G – JULY 2011 – REVISED APRIL 2013 www.ti.com 3.11 Converter Electrical Characteristics Power Supply Characteristics Symbol IA Parameter Conditions Analog Supply Current ITC IDR ADC12D1000RF Typ Lim Units (Limits) 1225 1140 mA 670 625 mA PDI = High; PDQ = Low 670 625 mA PDI = PDQ = High 2.7 2.
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ADC12D1000RF, ADC12D1600RF www.ti.com 4 SNAS519G – JULY 2011 – REVISED APRIL 2013 Specification Definitions APERTURE (SAMPLING) DELAY is the amount of delay, measured from the sampling edge of the CLK input, after which the signal present at the input pin is sampled inside the device. APERTURE JITTER (tAJ) is the variation in aperture delay from sample-to-sample. Aperture jitter can be effectively considered as noise at the input.
ADC12D1000RF, ADC12D1600RF SNAS519G – JULY 2011 – REVISED APRIL 2013 www.ti.com VD+ VDVOS ½×VOD VD+ VD - GND ½×VOD = | VD+ - VD- | Figure 4-1. LVDS Output Signal Levels LVDS OUTPUT OFFSET VOLTAGE (VOS) is the midpoint between the D+ and D- pins output voltage with respect to ground; i.e., [(VD+) +( VD-)]/2. See Figure 4-1. MISSING CODES are those output codes that are skipped and will never appear at the ADC outputs. These codes cannot be reached with any input value.
ADC12D1000RF, ADC12D1600RF www.ti.com SNAS519G – JULY 2011 – REVISED APRIL 2013 θJA is the thermal resistance between the junction to ambient. θJC1 represents the thermal resistance between the die and the exposed metal area on the top of the HSBGA package. θJC2 represents the thermal resistance between the die and the center group of balls on the bottom of the HSBGA package.
ADC12D1000RF, ADC12D1600RF SNAS519G – JULY 2011 – REVISED APRIL 2013 4.2 www.ti.com Timing Diagrams Sample N DI Sample N-1 DId VINI+/- Sample N+1 tAD CLK+ tOD DId, DI Sample N-39 and Sample N-38 Sample N-37 and Sample N-36 Sample N-35 and Sample N-34 tOSK DCLKI+/(0° Phase) tSU tH DCLKI+/(90° Phase) Figure 4-3.
ADC12D1000RF, ADC12D1600RF www.ti.com SNAS519G – JULY 2011 – REVISED APRIL 2013 DId DQd VINQ+/- c Sample N-1.5 Sample N-1 DQ DI c c Sample N Sample N-0.5 c Sample N+1 tAD c c CLK+/tOD DQd, DId, DQ, DI Sample N-37.5, N-37, N-36.5, N-36 Sample N-39.5, N-39, N-38.5, N-38 Sample N-35.5, N-35, N-34.5, N-34 tOSK DCLKQ+/(0° Phase) tSU tH DCLKQ+/(90° Phase) Figure 4-5. Clocking in 1:4 Demux DES Mode* Sample N-1 DI Sample N - 0.5 DQ Sample N DI VINQ+/- Sample N + 0.
ADC12D1000RF, ADC12D1600RF SNAS519G – JULY 2011 – REVISED APRIL 2013 www.ti.com Synchronizing Edge tSYNC_DLY CLK tHR tSR DCLK_RSTtOD DCLK_RST+ tPWR DCLKI+ DCLKQ+ Figure 4-7. Data Clock Reset Timing (Demux Mode) tCAL tCAL CalRun tCAL_H tCalDly Calibration Delay determined by CalDly (Pin V4) CAL tCAL_L POWER SUPPLY Figure 4-8.
ADC12D1000RF, ADC12D1600RF www.ti.com 5 SNAS519G – JULY 2011 – REVISED APRIL 2013 Typical Performance Plots INL vs. CODE (ADC12D1600RF) INL vs. CODE (ADC12D1000RF) 3 3 2 2 1 1 INL (LSB) INL (LSB) VA = VDR = VTC = VE = 1.9V, fCLK = 1600 MHz / 1000 MHz for the ADC12D1600RF / ADC12D1000RF, respectively, fIN = 498 MHz, TA= 25°C, I-channel, Demux Non-DES Mode, unless otherwise stated. 0 0 -1 -1 -2 -2 -3 -3 0 4095 0 OUTPUT CODE 4095 TEMPERATURE (°C) Figure 5-1. Figure 5-2. INL vs.
ADC12D1000RF, ADC12D1600RF www.ti.com DNL vs. TEMPERATURE (ADC12D1600RF) DNL vs. TEMPERATURE (ADC12D1000RF) 0.50 0.50 0.25 0.25 DNL (LSB) DNL (LSB) SNAS519G – JULY 2011 – REVISED APRIL 2013 0.00 -0.25 0.00 -0.25 +DNL -DNL -0.50 -50 0 50 +DNL -DNL 100 -0.50 -50 0 TEMPERATURE (°C) 50 100 TEMPERATURE (°C) Figure 5-7. Figure 5-8. ENOB vs. TEMPERATURE (ADC12D1600RF) ENOB vs.
ADC12D1000RF, ADC12D1600RF www.ti.com SNAS519G – JULY 2011 – REVISED APRIL 2013 ENOB vs. VCMI (ADC12D1000RF) 10 SNR vs. TEMPERATURE (ADC12D1600RF) 60 NON-DES MODE DES MODE 58 SNR (dB) ENOB 9 8 7 56 54 52 NON-DES MODE DES MODE 6 50 0.75 1.00 1.25 VCMI(V) 1.50 1.75 -50 0 50 TEMPERATURE (°C) 100 Figure 5-13. Figure 5-14. SNR vs. SUPPLY VOLTAGE (ADC12D1600RF) SNR vs. INPUT FREQUENCY (ADC12D1600RF) 60 60 55 SNR (dB) SNR (dB) 58 56 54 50 45 52 NON-DES MODE DES MODE 50 1.
ADC12D1000RF, ADC12D1600RF SNAS519G – JULY 2011 – REVISED APRIL 2013 www.ti.com THD vs. INPUT FREQUENCY (ADC12D1600RF) -40 SFDR vs. TEMPERATURE (ADC12D1600RF) 80 NON-DES MODE DES MODE NON-DES MODE DES MODE 70 SFDR (dBc) THD (dBc) -50 -60 60 -70 50 -80 40 0 1000 2000 INPUT FREQUENCY (MHz) 3000 -50 0 50 TEMPERATURE (°C) 100 Figure 5-19. Figure 5-20. SFDR vs. SUPPLY VOLTAGE (ADC12D1600RF) SFDR vs.
ADC12D1000RF, ADC12D1600RF www.ti.com SNAS519G – JULY 2011 – REVISED APRIL 2013 POWER CONSUMPTION vs. CLOCK FREQUENCY (ADC12D1600RF) INSERTION LOSS (ADC12D1x00RF) 5.0 0 4.5 POWER (W) -3 SIGNAL GAIN (dB) DEMUX MODE NON-DEMUX MODE -6 -9 -12 0 1000 2000 3000 INPUT FREQUENCY (MHz) 3.5 3.0 2.5 DESI MODE DESIQ MODE NON-DES, DESCLKIQ MODE -15 4.0 2.0 4000 0 400 800 1200 CLOCK FREQUENCY (MHz) Figure 5-25. 1600 Figure 5-26. POWER CONSUMPTION vs. CLOCK FREQUENCY (ADC12D1000RF) 5.
ADC12D1000RF, ADC12D1600RF SNAS519G – JULY 2011 – REVISED APRIL 2013 6 www.ti.com Functional Description The ADC12D1600/1000RF is a versatile A/D converter with an innovative architecture which permits very high speed operation. The controls available ease the application of the device to circuit solutions. Optimum performance requires adherence to the provisions discussed here and in the Applications Information Section.
ADC12D1000RF, ADC12D1600RF www.ti.com SNAS519G – JULY 2011 – REVISED APRIL 2013 Table 6-1.
ADC12D1000RF, ADC12D1600RF SNAS519G – JULY 2011 – REVISED APRIL 2013 6.2.1.4 www.ti.com Calibration Pin (CAL) The Calibration (CAL) Pin may be used to execute an on-command calibration or to disable the power-on calibration. The effect of calibration is to maximize the dynamic performance. To initiate an on-command calibration via the CAL pin, bring the CAL pin high for a minimum of tCAL_H input clock cycles after it has been low for a minimum of tCAL_L input clock cycles.
ADC12D1000RF, ADC12D1600RF www.ti.com SNAS519G – JULY 2011 – REVISED APRIL 2013 To use this feature in ECM, use the Configuration Registers (Addr: 3h and Bh). See Input Control and Adjust for more information. 6.2.1.10 AC/DC-Coupled Mode Pin (VCMO) The VCMO Pin serves a dual purpose. When functioning as an output, it provides the optimal commonmode voltage for the DC-coupled analog inputs. When functioning as an input, it selects whether the device is AC-coupled (logic-low) or DC-coupled (floating).
ADC12D1000RF, ADC12D1600RF SNAS519G – JULY 2011 – REVISED APRIL 2013 www.ti.com SCLK: This signal is used to register the input data (SDI) on the rising edge; and to source the output data (SDO) on the falling edge. The user may disable the clock and hold it at logic-low. There is no minimum frequency requirement for SCLK; see fSCLK in Converter Electrical Characteristics Serial Port Interface for more details.
ADC12D1000RF, ADC12D1600RF www.ti.com SNAS519G – JULY 2011 – REVISED APRIL 2013 1 2 3 4 5 6 7 8 R/W 1 0 A3 A2 A1 A0 X 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 25 SCSb SCLK SDI SDO Figure 6-2. Serial Data Protocol - Write Operation 6.3 FEATURES The ADC12D1600/1000RF offers many features to make the device convenient to use in a wide variety of applications.
ADC12D1000RF, ADC12D1600RF SNAS519G – JULY 2011 – REVISED APRIL 2013 www.ti.com Table 6-4.
ADC12D1000RF, ADC12D1600RF www.ti.com 6.3.1.4 SNAS519G – JULY 2011 – REVISED APRIL 2013 DES/Non-DES Mode The ADC12D1600/1000RF can operate in Dual-Edge Sampling (DES) or Non-DES Mode. The DES Mode allows for a single analog input to be sampled by both I- and Q-channels. One channel samples the input on the rising edge of the sampling clock and the other samples the same input signal on the falling edge of the sampling clock.
ADC12D1000RF, ADC12D1600RF SNAS519G – JULY 2011 – REVISED APRIL 2013 6.3.1.6 www.ti.com Sampling Clock Phase Adjust The sampling clock (CLK) phase may be delayed internally to the ADC up to 825 ps in ECM. This feature is intended to help the system designer remove small imbalances in clock distribution traces at the board level when multiple ADCs are used, or to simplify complex system functions such as beam steering for phase array antennas.
ADC12D1000RF, ADC12D1600RF www.ti.com SNAS519G – JULY 2011 – REVISED APRIL 2013 Data DCLK SDR Rising DCLK SDR Falling Figure 6-4. SDR DCLK-to-Data Phase Relationship 6.3.2.2 LVDS Output Differential Voltage The ADC12D1600/1000RF is available with a selectable higher or lower LVDS output differential voltage. This parameter is VOD and may be found in Converter Electrical Characteristics Digital Control and Output Pin Characteristics.
ADC12D1000RF, ADC12D1600RF SNAS519G – JULY 2011 – REVISED APRIL 2013 6.3.2.6 www.ti.com Test Pattern Mode The ADC12D1600/1000RF can provide a test pattern at the four output buses independently of the input signal to aid in system debug. In Test Pattern Mode, the ADC is disengaged and a test pattern generator is connected to the outputs, including ORI and ORQ. The test pattern output is the same in DES Mode or Non-DES Mode. Each port is given a unique 12-bit word, alternating between 1's and 0's.
ADC12D1000RF, ADC12D1600RF www.ti.com 6.3.2.7 SNAS519G – JULY 2011 – REVISED APRIL 2013 Time Stamp The Time Stamp feature enables the user to capture the timing of an external trigger event, relative to the sampled signal. When enabled via the TSE Bit (Addr: 0h; Bit: 3), the LSB of the digital outputs (DQd, DQ, DId, DI) captures the trigger information. In effect, the 12-bit converter becomes an 11-bit converter and the LSB acts as a 1-bit converter with the same latency as the 11-bit converter.
ADC12D1000RF, ADC12D1600RF SNAS519G – JULY 2011 – REVISED APRIL 2013 www.ti.com The power-on calibration will be not be performed if the CAL pin is logic-high at power-on. In this case, the calibration cycle will not begin until the on-command calibration conditions are met. The ADC12D1600/1000RF will function with the CAL pin held high at power up, but no calibration will be done and performance will be impaired.
ADC12D1000RF, ADC12D1600RF www.ti.com SNAS519G – JULY 2011 – REVISED APRIL 2013 5. Continue with normal operation. To write calibration values to the SPI, do the following: 1. Set ADC to operating conditions at which Calibration Values were previously read. 2. Set SSC (Addr: 4h, Bit 7) to 1. 3. Write exactly 239 times the Calibration Values register (Addr: 5h). The registers should be written with stored register values R1, R2... R239. 4. Make two additional dummy writes of 0000h. 5.
ADC12D1000RF, ADC12D1600RF SNAS519G – JULY 2011 – REVISED APRIL 2013 www.ti.com samples data on the falling edge of CLK+. The digital equivalent of that data is available at the digital outputs a constant number of sampling clock cycles later for the DI, DQ, DId and DQd output buses, a.k.a. Latency, depending on the demultiplex mode which is selected. In addition to the Latency, there is a constant output delay, tOD, before the data is available at the outputs. See tOD in the Timing Diagrams.
ADC12D1000RF, ADC12D1600RF www.ti.com SNAS519G – JULY 2011 – REVISED APRIL 2013 Table 6-9. Unused Analog Input Recommended Termination 6.4.1.3 Mode Power Down Coupling Recommended Termination Non-DES Yes AC/DC Tie Unused+ and Unused- to Vbg DES/NonDES No DC Tie Unused+ and Unused- to Vbg DES/NonDES No AC Tie Unused+ to Unused- FSR and the Reference Voltage The full-scale analog differential input range (VIN_FSR) of the ADC12D1600/1000RF is derived from an internal bandgap reference.
ADC12D1000RF, ADC12D1600RF SNAS519G – JULY 2011 – REVISED APRIL 2013 www.ti.com When the AC-coupled Mode is selected, an analog input channel that is not used (e.g. in DES Mode) should be connected to AC ground, e.g. through capacitors to ground . Do not connect an unused analog input directly to ground. Ccouple VIN+ Ccouple VINVCMO ADC12D1600/1000RF Figure 6-6.
ADC12D1000RF, ADC12D1600RF www.ti.com 6.4.2 SNAS519G – JULY 2011 – REVISED APRIL 2013 THE CLOCK INPUTS The ADC12D1600/1000RF has a differential clock input, CLK+ and CLK-, which must be driven with an AC-coupled, differential clock signal. This provides the level shifting necessary to allow for the clock to be driven with LVDS, PECL, LVPECL, or CML levels. The clock inputs are internally terminated to 100Ω differential and self-biased.
ADC12D1000RF, ADC12D1600RF SNAS519G – JULY 2011 – REVISED APRIL 2013 6.4.2.5 www.ti.com CLK Jitter High speed, high performance ADCs such as the ADC12D1600/1000RF require a very stable input clock signal with minimum phase noise or jitter. ADC jitter requirements are defined by the ADC resolution (number of bits), maximum ADC input frequency and the input signal amplitude relative to the ADC input full scale range.
ADC12D1000RF, ADC12D1600RF www.ti.com 6.4.3.3 SNAS519G – JULY 2011 – REVISED APRIL 2013 Terminating Unused LVDS Output Pins If the ADC is used in Non-Demux Mode, then only the DI and DQ data outputs will have valid data present on them. The DId and DQd data outputs may be left not connected; if unused, they are internally tristated. Similarly, if the Q-channel is powered-down (i.e. PDQ is logic-high), the DQ data output pins, DCLKQ and ORQ may be left not connected. 6.4.
ADC12D1000RF, ADC12D1600RF SNAS519G – JULY 2011 – REVISED APRIL 2013 www.ti.com RCLK Slave 2 RCOut1 ADC12D1600/1000RF RCOut2 DCLK CLK RCLK CLK Slave 1 RCOut1 ADC12D1600/1000RF RCOut2 DCLK CLK RCLK Master RCOut1 ADC12D1600/1000RF RCOut2 DCLK CLK Figure 6-9. AutoSync Example In order to synchronize the DCLK (and Data) outputs of multiple ADCs, the DCLKs must transition at the same time, as well as be in phase with one another.
ADC12D1000RF, ADC12D1600RF www.ti.com 6.4.5 SNAS519G – JULY 2011 – REVISED APRIL 2013 SUPPLY/GROUNDING, LAYOUT AND THERMAL RECOMMENDATIONS 6.4.5.1 Power Planes All supply buses for the ADC should be sourced from a common linear voltage regulator. This ensures that all power buses to the ADC are turned on and off simultaneously. This single source will be split into individual sections of the power plane, with individual decoupling and connection to the different power supply buses of the ADC.
ADC12D1000RF, ADC12D1600RF SNAS519G – JULY 2011 – REVISED APRIL 2013 www.ti.com Linear Regulator Cross Section Line HV or Unreg Voltage Switching Regulator Intermediate Voltage 1.9V ADC Main VTC VA VE VDR ADC Top Layer ± Signal 1 Dielectric 1 Ground 1 Dielectric 2 Signal 2 Dielectric 3 Ground 2 Dielectric 4 Signal 3 Dielectric 5 Power 1 Dielectric 6 Ground 3 Dielectric 7 Bottom Layer ± Signal X Figure 6-10. Power and Grounding Example 6.4.5.
ADC12D1000RF, ADC12D1600RF www.ti.com SNAS519G – JULY 2011 – REVISED APRIL 2013 The center ground balls should be soldered down to the recommended ball pads (See AN-1126 (Literature Number SNOA021)). These balls will have wide traces which in turn have vias which connect to the internal ground planes, and a bottom ground pad/pour if possible. This ensures a good ground is provided for these balls, and that the optimal heat transfer will occur between these balls and the PCB ground planes.
ADC12D1000RF, ADC12D1600RF SNAS519G – JULY 2011 – REVISED APRIL 2013 www.ti.com Following the application of power to the ADC12D1600/1000RF, there is a delay of tCalDly and then the Power-on Calibration is executed. This is why it is recommended to set the CalDly Pin via an external pullup or pull-down resistor. This ensures that the state of that input will be properly set at the same time that power is applied to the ADC and tCalDly will be a known quantity.
ADC12D1000RF, ADC12D1600RF www.ti.com SNAS519G – JULY 2011 – REVISED APRIL 2013 FPGA writes Control Pins Power to ADC ADC output valid CalDly Calibration Power-on Calibration On-command Calibration Figure 6-13. Power-on with Control Pins set by FPGA pre Power-on Cal FPGA writes Control Pins Power to ADC CalDly Calibration Power-on Calibration On-command Calibration Figure 6-14. Power-on with Control Pins set by FPGA post Power-on Cal 6.4.6.
ADC12D1000RF, ADC12D1600RF www.ti.com mV SNAS519G – JULY 2011 – REVISED APRIL 2013 Slope = 1.22V/ms 1900 1710 VA 1490 1210 660 635 520 DCLK 300 time Figure 6-15. Supply and DCLK Ramping 6.4.7 RECOMMENDED SYSTEM CHIPS TI recommends these other chips including temperature sensors, clocking devices, and amplifiers in order to support the ADC12D1600/1000RF in a system design. 6.4.7.
ADC12D1000RF, ADC12D1600RF www.ti.com SNAS519G – JULY 2011 – REVISED APRIL 2013 In the following typical application, the LM95213 is used to monitor the temperature of an ADC12D1600/1000RF as well as an FPGA, see Figure 6-16. If this feature is unused, the Tdiode+/- pins may be left floating. 7 ADC12D1600/1000RF IE = IF D1+ 100 pF IR 5 IE = IF FPGA D- 100 pF 6 D2+ IR LM95213 Figure 6-16. Typical Temperature Sensor Application 6.4.7.
ADC12D1000RF, ADC12D1600RF SNAS519G – JULY 2011 – REVISED APRIL 2013 www.ti.com Table 6-13. Balun Recommendations 6.5 Balun Bandwidth Mini Circuits TC1-113MA+ 4.5 - 3000MHz Anaren B0430J50100A00 400 - 3000 MHz Mini Circuits ADTL218 30 - 1800 MHz Register Definitions Eleven read/write registers provide several control and configuration options in the Extended Control Mode. These registers have no effect when the device is in the Non-extended Control Mode.
ADC12D1000RF, ADC12D1600RF www.ti.com SNAS519G – JULY 2011 – REVISED APRIL 2013 Bit 12 TPM: Test Pattern Mode. When this bit is set to 1b, the device will continually output a fixed digital pattern at the digital Data and OR outputs. When set to 0b, the device will continually output the converted signal, which was present at the analog inputs. See Test Pattern Mode for details about the TPM pattern. Bit 11 PDI: Power-down I-channel.
ADC12D1000RF, ADC12D1600RF SNAS519G – JULY 2011 – REVISED APRIL 2013 www.ti.com 1000 0000 0000 22.5 1111 1111 1111 45 Table 6-18. I-channel Full Scale Range Adjust Addr: 3h (0011b) Bit 15 Name Res POR 0 POR state: 4000h 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 FM(14:0) 1 0 0 0 0 0 0 0 Bit 15 Reserved. Must be set to 0b. Bits 14:0 FM(14:0): FSR Magnitude. These bits increase the ADC full-scale range magnitude (straight binary coding.
ADC12D1000RF, ADC12D1600RF www.ti.com Bits 15:0 SNAS519G – JULY 2011 – REVISED APRIL 2013 Reserved. Must be set as shown. Table 6-22. DES Timing Adjust Addr: 7h (0111b) Bit POR state: 8142h 15 14 13 Name POR 12 11 10 9 8 7 6 5 DTA(6:0) 1 0 0 4 3 2 1 0 0 0 1 0 Res 0 0 0 0 1 0 1 0 0 Bits 15:9 DTA(6:0): DES Mode Timing Adjust.
ADC12D1000RF, ADC12D1600RF SNAS519G – JULY 2011 – REVISED APRIL 2013 www.ti.com Table 6-26. Q-channel Full-Scale Range Adjust Addr: Bh (1011b) Bit 15 Name Res POR 0 POR state: 4000h 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 FM(14:0) 1 0 0 0 0 0 0 0 Bit 15 Reserved. Must be set to 0b. Bits 14:0 FM(14:0): FSR Magnitude. These bits increase the ADC full-scale range magnitude (straight binary coding.
ADC12D1000RF, ADC12D1600RF www.ti.com SNAS519G – JULY 2011 – REVISED APRIL 2013 Table 6-29. AutoSync (1) Addr: Eh (1110b) Bit 15 POR state: 0003h 14 13 12 Name POR 11 10 9 8 7 DRC(8:0) 0 0 0 0 0 0 0 0 0 6 5 DCK Res 0 0 4 3 SP(1:0) 0 0 2 1 0 ES DOC DR 0 1 1 (1) This feature functionality is not tested in production test; performance is tested in the specified/default mode only. Bits 15:7 DRC(8:0): Delay Reference Clock (8:0).
ADC12D1000RF, ADC12D1600RF SNAS519G – JULY 2011 – REVISED APRIL 2013 www.ti.com Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (April 2013) to Revision G • 70 Changed layout of National Data Sheet to TI format Functional Description Page ..........................................................................
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