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ADC12D1800RF

ADC12D1800RF 12-Bit, Single 3.6 GSPS RF Sampling ADC

Data Manual

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Literature Number: SNAS518I

July 2011–Revised JANUARY 2014

Summary of content (80 pages)

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ADC12D1800RF ADC12D1800RF 12-Bit, Single 3.6 GSPS RF Sampling ADC Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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ADC12D1800RF www.ti.com SNAS518I – JULY 2011 – REVISED JANUARY 2014 Contents 1 Introduction 1.1 1.2 1.3 2 3 .............................................................................................................. 8 2.1 Block Diagram ............................................................................................................... 8 2.2 RF Performance ............................................................................................................. 9 2.
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ADC12D1800RF www.ti.com SNAS518I – JULY 2011 – REVISED JANUARY 2014 Extended Control Mode ........................................................................................ 6.2.2.1 The Serial Interface ................................................................................ FEATURES ................................................................................................................. 6.3.1 Input Control and Adjust ...................................................................
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 6.5 6.4.5.1 Power Planes ....................................................................................... 6.4.5.2 Bypass Capacitors ................................................................................. 6.4.5.3 Ground Planes ..................................................................................... 6.4.5.4 Power System Example ........................................................................... 6.4.5.
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ADC12D1800RF www.ti.com SNAS518I – JULY 2011 – REVISED JANUARY 2014 List of Figures 2-1 ADC12D1800RF Non-DES Mode IMD3......................................................................................... 9 2-2 ADC12D1800RF DES Mode FFT .............................................................................................. 10 2-3 ADC12D1800RF Connection Diagram ........................................................................................ 10 4-1 LVDS Output Signal Levels ....
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 www.ti.com List of Tables 2-1 Analog Front-End and Clock Balls ............................................................................................. 11 2-2 Control and Status Balls ......................................................................................................... 13 2-3 Power and Ground Balls ........................................................................................................
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ADC12D1800RF www.ti.com SNAS518I – JULY 2011 – REVISED JANUARY 2014 ADC12D1800RF 12-Bit, Single 3.6 GSPS RF Sampling ADC Check for Samples: ADC12D1800RF 1 Introduction 1.1 Features 12 • Excellent Noise and Linearity up to and Above fIN = 2.7 GHz • Configurable to Either 3.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 2 Device Information 2.1 Block Diagram 8 Device Information www.ti.
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ADC12D1800RF www.ti.com 2.2 SNAS518I – JULY 2011 – REVISED JANUARY 2014 RF Performance -40 -7 dBFS -10 dBFS -13 dBFS -16 dBFS IMD3(dBFS) -50 -60 -70 -80 -90 -100 0 1 2 3 INPUT FREQUENCY (GHz) 4 CW Blocker: Fin = 2675 MHz; Total Power = -13 dBFS WCDMA Blocker: Fc = 2685 MHz; Bandwidth = 3.84 MHz; Total Power = -13 dBFS IMD3 Product Power = -75 dBFS Figure 2-1. ADC12D1800RF Non-DES Mode IMD3 0 MAGNITUDE (dBFS) Fin = 2.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 2.3 www.ti.
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ADC12D1800RF www.ti.com 2.4 SNAS518I – JULY 2011 – REVISED JANUARY 2014 Ball Descriptions and Equivalent Circuits Table 2-1. Analog Front-End and Clock Balls Ball No. Name Equivalent Circuit Description Differential signal I- and Q-inputs. In the Non-Dual Edge Sampling (Non-DES) Mode, each I- and Qinput is sampled and converted by its respective channel with each positive transition of the CLK input. In Non-ECM (Non-Extended Control Mode) and DES Mode, both channels sample the I-input.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 www.ti.com Table 2-1. Analog Front-End and Clock Balls (continued) Ball No. Name Equivalent Circuit Description VA VCMO C2 200k VCMO Enable AC Coupling 8 pF GND Bandgap Voltage Output or LVDS Common-mode Voltage Select. This pin provides a buffered version of the bandgap output voltage and is capable of sourcing / sinking 100 uA and driving a load of up to 80 pF.
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ADC12D1800RF www.ti.com SNAS518I – JULY 2011 – REVISED JANUARY 2014 Table 2-1. Analog Front-End and Clock Balls (continued) Ball No. Name Equivalent Circuit Description VA Y4/W5 50k AGND RCLK+/- 100 VA VBIAS 50k Reference Clock Input. When the AutoSync feature is active, and the ADC12D1800RF is in Slave Mode, the internal divided clocks are synchronized with respect to this input clock. The delay on this clock may be adjusted when synchronizing multiple ADCs.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 www.ti.com Table 2-2. Control and Status Balls (continued) Ball No. Name Equivalent Circuit VA D6 CAL GND Description Calibration cycle initiate. The user can command the device to execute a self-calibration cycle by holding this input high a minimum of tCAL_H after having held it low a minimum of tCAL_L.
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ADC12D1800RF www.ti.com SNAS518I – JULY 2011 – REVISED JANUARY 2014 Table 2-2. Control and Status Balls (continued) Ball No. Name Equivalent Circuit VA Y3 FSR GND VA W4 DDRPh GND Description Full-Scale input Range select. In Non-ECM, this input must be set to logic-high; the full-scale differential input range for both I- and Q-channel inputs is set by this pin.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 www.ti.com Table 2-2. Control and Status Balls (continued) Ball No. Name Equivalent Circuit Description VA 100 k: B4 Serial Data-In. In ECM, serial data is shifted into the device on this pin while SCS signal is asserted (logic-low). SDI GND VA A3 Serial Data-Out. In ECM, serial data is shifted out of the device on this pin while SCS signal is asserted (logic-low). This output is at TRI-STATE when SCS is de-asserted.
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ADC12D1800RF www.ti.com SNAS518I – JULY 2011 – REVISED JANUARY 2014 Table 2-3. Power and Ground Balls (continued) Ball No. Name Equivalent Circuit A1, A7, B2, B7, D4, D5, E4, K1, L1, T4, U4, U5, W2, W7, Y1, Y7, H8:N13 Description GND NONE Ground Return for the Analog circuitry. F2, G2, H3, J2, K4, L4, M2, N3, P2, R2, T2, T3, U1 GNDTC NONE Ground Return for the Track-and-Hold and Clock circuitry.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 www.ti.com Table 2-4. High-Speed Digital Outputs (continued) 18 Ball No.
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ADC12D1800RF www.ti.com SNAS518I – JULY 2011 – REVISED JANUARY 2014 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 3 Electrical Specifications 3.1 Absolute Maximum Ratings (1) (2) Supply Voltage (VA, VTC, VDR, VE) 2.2V Supply Difference max(VA/TC/DR/E)- min(VA/TC/DR/E) 0V to 100 mV Voltage on Any Input Pin (except VIN+/-) −0.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 www.ti.com Operating Ratings(1)(2) (continued) VIN+/- Power 15.3 dBm (maintaining common mode voltage, a.c.-coupled) 17.1 dBm (not maintaining common mode voltage, a.c.-coupled) Ground Difference max(GNDTC/DR/E) -min(GNDTC/DR/E) 0V CLK+/- Voltage Range 0V to VA Differential CLK Amplitude 0.4VP-P to 2.0VP-P Common Mode Input Voltage Package Thermal Resistance (1) 3.
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ADC12D1800RF www.ti.com 3.5 SNAS518I – JULY 2011 – REVISED JANUARY 2014 Converter Electrical Characteristics Dynamic Converter Characteristics (1) Symbol Parameter Bandwidth Conditions ADC12D1800RF Typ Lim Units (Limits) Non-DES Mode, DESCLKIQ Mode -3 dB (2) 2.7 GHz -6 dB 3.1 GHz -9 dB 3.5 GHz -12 dB 4.0 GHz -3 dB (2) 1.2 GHz -6 dB 2.3 GHz -9 dB 2.7 GHz -12 dB 3.0 GHz -3 dB (2) 1.75 GHz -6 dB 2.7 GHz D.C. to Fs/2 ±0.4 dB D.C. to Fs ±1.1 dB D.C. to 3Fs/2 ±1.
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ADC12D1800RF www.ti.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 3.6 www.ti.
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ADC12D1800RF www.ti.com 3.7 Converter Electrical Characteristics I-Channel to Q-Channel Characteristics Symbol X-TALK (1) SNAS518I – JULY 2011 – REVISED JANUARY 2014 Parameter Conditions (1) Lim Units (Limits) Offset Match See 2 LSB Positive Full-Scale Match Zero offset selected in Control Register 2 LSB Negative Full-Scale Match Zero offset selected in Control Register 2 LSB Phase Matching (I, Q) fIN = 1.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 www.ti.com 3.10 Converter Electrical Characteristics Digital Control and Output Pin Characteristics Symbol Parameter ADC12D1800RF Conditions Typ Lim Units (Limits) Digital Control Pins (DES, CalDly, CAL, PDI, PDQ, TPM, NDM, FSR, DDRPh, ECE, SCLK, SDI, SCS) VIH Logic High Input Voltage 0.7×VA V (min) VIL Logic Low Input Voltage 0.3×VA V (max) IIH Input Leakage Current; VIN = VA IIL Input Leakage Current; VIN = GND CIN_DIG 0.
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ADC12D1800RF www.ti.com SNAS518I – JULY 2011 – REVISED JANUARY 2014 3.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 www.ti.
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ADC12D1800RF www.ti.com SNAS518I – JULY 2011 – REVISED JANUARY 2014 3.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 4 www.ti.com Specification Definitions APERTURE JITTER (tAJ) is the variation in aperture delay from sample-to-sample. Aperture jitter can be effectively considered as noise at the input. CODE ERROR RATE (CER) is the probability of error and is defined as the probable number of word errors on the ADC output per unit of time divided by the number of words seen in that amount of time.
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ADC12D1800RF www.ti.com SNAS518I – JULY 2011 – REVISED JANUARY 2014 LVDS OUTPUT OFFSET VOLTAGE (VOS) is the midpoint between the D+ and D- pins output voltage with respect to ground; i.e., [(VD+) +( VD-)]/2. See Figure 4-1. MISSING CODES are those output codes that are skipped and will never appear at the ADC outputs. These codes cannot be reached with any input value. MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 www.ti.com TOTAL HARMONIC DISTORTION (THD) is the ratio expressed in dB, of the rms total of the first nine harmonic levels at the output to the level of the fundamental at the output. THD is calculated as A 2 +... +A 2 f2 f10 A f12 THD = 20 x log where Af1 is the RMS power of the fundamental (output) frequency and Af2 through Af10 are the RMS power of the first 9 harmonic frequencies in the output spectrum.
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ADC12D1800RF www.ti.com 4.2 SNAS518I – JULY 2011 – REVISED JANUARY 2014 Timing Diagrams Sample N DI Sample N-1 DId VINI+/- Sample N+1 tAD CLK+ tOD DId, DI Sample N-39 and Sample N-38 Sample N-37 and Sample N-36 Sample N-35 and Sample N-34 tOSK DCLKI+/(0° Phase) tSU tH DCLKI+/(90° Phase) Figure 4-3.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 DId VINQ+/- DQd c Sample N-1.5 Sample N-1 www.ti.com DQ DI c c Sample N Sample N-0.5 c Sample N+1 tAD c c CLK+/tOD DQd, DId, DQ, DI Sample N-37.5, N-37, N-36.5, N-36 Sample N-39.5, N-39, N-38.5, N-38 Sample N-35.5, N-35, N-34.5, N-34 tOSK DCLKQ+/(0° Phase) tSU tH DCLKQ+/(90° Phase) Figure 4-5. Clocking in 1:4 Demux DES Mode* Sample N-1 DI Sample N - 0.5 DQ Sample N DI VINQ+/- Sample N + 0.
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ADC12D1800RF www.ti.com SNAS518I – JULY 2011 – REVISED JANUARY 2014 Synchronizing Edge tSYNC_DLY CLK tHR tSR DCLK_RSTtOD DCLK_RST+ tPWR DCLKI+ DCLKQ+ Figure 4-7. Data Clock Reset Timing (Demux Mode) tCAL tCAL CalRun tCAL_H tCalDly Calibration Delay determined by CalDly (Pin V4) CAL tCAL_L POWER SUPPLY Figure 4-8.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 5 www.ti.com Typical Performance Plots VA = VDR = VTC = VE = 1.9V, fCLK = 1.8 GHz, fIN = 498 MHz, TA= 25°C, I-channel, 1:2 Demux Non-DES Mode (1:1 Demux Non-DES Mode has similar performance), unless otherwise stated. INL vs. CODE (ADC12D1800RF) INL vs. TEMPERATURE (ADC12D1800RF) 3 1.0 +INL -INL 2 INL (LSB) INL (LSB) 0.5 1 0 0.0 -1 -0.5 -2 -3 -1.0 0 4095 -50 OUTPUT CODE 0 50 TEMPERATURE (°C) 100 Figure 5-1. Figure 5-2. DNL vs.
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ADC12D1800RF www.ti.com SNAS518I – JULY 2011 – REVISED JANUARY 2014 ENOB vs. CLOCK FREQUENCY (ADC12D1800RF) 10 ENOB vs. INPUT FREQUENCY (ADC12D1800RF) 10 NON-DES MODE DES MODE 9 ENOB ENOB 9 8 7 7 6 NON-DES MODE DES MODE 6 0 600 1200 CLOCK FREQUENCY (MHz) 1800 0 1000 2000 INPUT FREQUENCY (MHz) 3000 Figure 5-7. Figure 5-8. ENOB vs. VCMI (ADC12D1800RF) SNR vs.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 www.ti.com SNR vs. INPUT FREQUENCY (ADC12D1800RF) THD vs. TEMPERATURE (ADC12D1800RF) 60 -40 -50 SNR (dB) THD (dBc) 55 -60 50 -70 NON-DES MODE DES MODE 45 0 1000 2000 INPUT FREQUENCY (MHz) 3000 -50 0 50 TEMPERATURE (°C) 100 Figure 5-14. THD vs. SUPPLY VOLTAGE (ADC12D1800RF) THD vs. CLOCK FREQUENCY (ADC12D1800RF) -40 -40 -50 -50 THD (dBc) THD (dBc) Figure 5-13.
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ADC12D1800RF www.ti.com SNAS518I – JULY 2011 – REVISED JANUARY 2014 SFDR vs. CLOCK FREQUENCY (ADC12D1800RF) 80 80 70 70 SFDR (dBc) SFDR (dBc) SFDR vs. SUPPLY VOLTAGE (ADC12D1800RF) 60 50 NON-DES MODE DES MODE 60 50 NON-DES MODE DES MODE 40 1.8 1.9 2.0 VA(V) 40 2.1 2.2 0 600 1200 CLOCK FREQUENCY (MHz) 1800 Figure 5-20. SFDR vs. INPUT FREQUENCY (ADC12D1800RF) SPECTRAL RESPONSE NON-DES MODE (ADC12D1800RF) 80 0 70 -25 AMPLITUDE (dBFS) SFDR (dBc) Figure 5-19.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 www.ti.com CROSSTALK vs. SOURCE FREQUENCY (ADC12D1800RF) -30 INSERTION LOSS (ADC12D1800RF) 0 NON-DES MODE -3 SIGNAL GAIN (dB) CROSSTALK (dB) -40 -50 -60 -70 -6 -9 -12 -80 -90 DESI MODE DESIQ MODE NON-DES, DESCLKIQ MODE -15 0 1000 2000 3000 AGGRESSOR INPUT FREQUENCY (MHz) 0 Figure 5-25. 1000 2000 3000 INPUT FREQUENCY (MHz) 4000 Figure 5-26. POWER CONSUMPTION vs. CLOCK FREQUENCY (ADC12D1800RF) 5.
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ADC12D1800RF www.ti.com 6 SNAS518I – JULY 2011 – REVISED JANUARY 2014 Functional Description The ADC12D1800RF is a versatile A/D converter with an innovative architecture which permits very high speed operation. The controls available ease the application of the device to circuit solutions. Optimum performance requires adherence to the provisions discussed here and in the Applications Information section.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 www.ti.com Table 6-1.
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ADC12D1800RF www.ti.com 6.2.1.4 SNAS518I – JULY 2011 – REVISED JANUARY 2014 Calibration Pin (CAL) The Calibration (CAL) Pin may be used to execute an on-command calibration or to disable the power-on calibration. The effect of calibration is to maximize the dynamic performance. To initiate an on-command calibration via the CAL pin, bring the CAL pin high for a minimum of tCAL_H input clock cycles after it has been low for a minimum of tCAL_L input clock cycles.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 www.ti.com To use this feature in ECM, use the Configuration Registers (Addr: 3h and Bh). See Input Control and Adjust for more information. 6.2.1.10 AC / DC-Coupled Mode Pin (VCMO) The VCMO Pin serves a dual purpose. When functioning as an output, it provides the optimal commonmode voltage for the DC-coupled analog inputs. When functioning as an input, it selects whether the device is AC-coupled (logic-low) or DC-coupled (floating).
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ADC12D1800RF www.ti.com SNAS518I – JULY 2011 – REVISED JANUARY 2014 SCLK: This signal is used to register the input data (SDI) on the rising edge; and to source the output data (SDO) on the falling edge. The user may disable the clock and hold it at logic-low. There is no minimum frequency requirement for SCLK; see fSCLK in Converter Electrical Characteristics Serial Port Interface for more details.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 www.ti.com 1 2 3 4 5 6 7 8 R/W 1 0 A3 A2 A1 A0 X 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 25 SCSb SCLK SDI SDO Figure 6-2. Serial Data Protocol - Write Operation 6.3 FEATURES The ADC12D1800RF offers many features to make the device convenient to use in a wide variety of applications.
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ADC12D1800RF www.ti.com SNAS518I – JULY 2011 – REVISED JANUARY 2014 Table 6-4.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 6.3.1.3 www.ti.com Input Offset Adjust The input offset adjust for the ADC12D1800RF may be adjusted with 12-bits of precision plus sign via ECM. See Register Definitions for information about the registers. 6.3.1.4 DES/Non-DES Mode The ADC12D1800RF can operate in Dual-Edge Sampling (DES) or Non-DES Mode. The DES Mode allows for a single analog input to be sampled by both I- and Q-channels.
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ADC12D1800RF www.ti.com 6.3.1.6 SNAS518I – JULY 2011 – REVISED JANUARY 2014 Sampling Clock Phase (Aperture) Delay Adjust NOTE Sampling Clock Phase Adjust cannot be used in DES mode (DESI, DESQ, DESIQ or DESCLKIQ) at CLK frequencies above 1600 MHz. The sampling clock (CLK) phase may be delayed internally to the ADC up to 825 ps in ECM.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 www.ti.com For SDR, the DCLK frequency is the same as the data rate and data is sent to the outputs on a single edge of DCLK; see Figure 6-4. The Data may transition on either rising or falling edge of DCLK. Any offset from this timing is tOSK; see Converter Electrical Characteristics AC Electrical Characteristics for details. The DCLK rising / falling edge may be selected via the SDR bit in the Configuration Register (Addr: 0h; Bit: 2) in ECM only.
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ADC12D1800RF www.ti.com SNAS518I – JULY 2011 – REVISED JANUARY 2014 Table 6-5. Supported Demux, Data Rate Modes 6.3.2.6 Non-Demux Mode 1:2 Demux Mode DDR 0° Mode only 0° Mode / 90° Mode SDR Not Available Rising / Falling Mode Test Pattern Mode The ADC12D1800RF can provide a test pattern at the four output buses independently of the input signal to aid in system debug. In Test Pattern Mode, the ADC is disengaged and a test pattern generator is connected to the outputs, including ORI and ORQ.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 www.ti.com Table 6-7. Test Pattern by Output Port in Non-Demux Mode (continued) 6.3.2.7 Time Q I ORQ ORI T10 000h 004h 0b 0b T11 000h 004h 0b 0b T12 FFFh FFBh 1b 1b T13 FFFh FFBh 1b 1b T14 ... ... ... ... Comments Pattern Sequence n+1 Time Stamp The Time Stamp feature enables the user to capture the timing of an external trigger event, relative to the sampled signal.
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ADC12D1800RF www.ti.com 6.3.3.3 SNAS518I – JULY 2011 – REVISED JANUARY 2014 Power-on Calibration For standard operation, power-on calibration begins after a time delay following the application of power, as determined by the setting of the CalDly Pin and measured by tCalDly (see Converter Electrical Characteristics Calibration). This delay allows the power supply to come up and stabilize before the power-on calibration takes place.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 6.3.3.6 www.ti.com Read / Write Calibration Settings When the ADC performs a calibration, the calibration constants are stored in an array which is accessible via the Calibration Values register (Addr: 5h). To save the time which it takes to execute a calibration, tCAL, or to allow for re-use of a previous calibration result, these values can be read from and written to the register at a later time.
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ADC12D1800RF www.ti.com 6.4 SNAS518I – JULY 2011 – REVISED JANUARY 2014 Applications Information 6.4.1 THE ANALOG INPUTS The ADC12D1800RF will continuously convert any signal which is present at the analog inputs, as long as a CLK signal is also provided to the device. This section covers important aspects related to the analog inputs including: acquiring the input, driving the ADC in DES Mode, the reference voltage and FSR, out-ofrange indication, AC/DC-coupled signals, and single-ended input signals.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 www.ti.com In the case that only one channel is used in Non-DES Mode or that the ADC is driven in DESI or DESQ Mode, the unused analog input should be terminated to reduce any noise coupling into the ADC. See Table 6-9 for details. Table 6-9. Unused Analog Input Recommended Termination 6.4.1.
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ADC12D1800RF www.ti.com SNAS518I – JULY 2011 – REVISED JANUARY 2014 In AC-coupled Mode, the analog inputs must of course be AC-coupled. For an ADC12D1800RF used in a typical application, this may be accomplished by on-board capacitors, as shown in Figure 6-6. For the ADC12D1800RFRB, the SMA inputs on the Reference Board are directly connected to the analog inputs on the ADC12D1800RF, so this may be accomplished by DC blocks (included with the hardware kit).
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 6.4.2 www.ti.com THE CLOCK INPUTS The ADC12D1800RF has a differential clock input, CLK+ and CLK-, which must be driven with an ACcoupled, differential clock signal. This provides the level shifting necessary to allow for the clock to be driven with LVDS, PECL, LVPECL, or CML levels. The clock inputs are internally terminated to 100Ω differential and self-biased.
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ADC12D1800RF www.ti.com 6.4.2.5 SNAS518I – JULY 2011 – REVISED JANUARY 2014 CLK Jitter High speed, high performance ADCs such as the ADC12D1800RF require a very stable input clock signal with minimum phase noise or jitter. ADC jitter requirements are defined by the ADC resolution (number of bits), maximum ADC input frequency and the input signal amplitude relative to the ADC input full scale range.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 6.4.3.3 www.ti.com Terminating Unused LVDS Output Pins If the ADC is used in Non-Demux Mode, then only the DI and DQ data outputs will have valid data present on them. The DId and DQd data outputs may be left not connected; if unused, they are internally at TRISTATE. Similarly, if the Q-channel is powered-down (i.e. PDQ is logic-high), the DQ data output pins, DCLKQ and ORQ may be left not connected. 6.4.
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ADC12D1800RF www.ti.com SNAS518I – JULY 2011 – REVISED JANUARY 2014 Master ADC12D1XXX RCOut1 RCOut2 CLK DCLK Slave 2 ADC12D1XXX RCLK RCOut1 RCOut2 CLK RCLK Slave 1 ADC12D1XXX DCLK RCOut1 CLK RCLK RCOut2 DCLK CLK Figure 6-9. AutoSync Example In order to synchronize the DCLK (and Data) outputs of multiple ADCs, the DCLKs must transition at the same time, as well as be in phase with one another. The DCLK at each ADC is generated from the CLK after some latency, plus tOD minus tAD.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 6.4.5 www.ti.com SUPPLY / GROUNDING, LAYOUT AND THERMAL RECOMMENDATIONS 6.4.5.1 Power Planes All supply buses for the ADC should be sourced from a common linear voltage regulator. This ensures that all power buses to the ADC are turned on and off simultaneously. This single source will be split into individual sections of the power plane, with individual decoupling and connection to the different power supply buses of the ADC.
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ADC12D1800RF www.ti.com SNAS518I – JULY 2011 – REVISED JANUARY 2014 Linear Regulator Cross Section Line HV or Unreg Voltage Switching Regulator Intermediate Voltage 1.9V ADC Main VTC VA VE VDR ADC Top Layer ± Signal 1 Dielectric 1 Ground 1 Dielectric 2 Signal 2 Dielectric 3 Ground 2 Dielectric 4 Signal 3 Dielectric 5 Power 1 Dielectric 6 Ground 3 Dielectric 7 Bottom Layer ± Signal X Figure 6-10. Power and Grounding Example 6.4.5.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 www.ti.com The center ground balls should be soldered down to the recommended ball pads (See AN-1126). These balls will have wide traces which in turn have vias which connect to the internal ground planes, and a bottom ground pad / pour if possible. This ensures a good ground is provided for these balls, and that the optimal heat transfer will occur between these balls and the PCB ground planes.
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ADC12D1800RF www.ti.com SNAS518I – JULY 2011 – REVISED JANUARY 2014 Following the application of power to the ADC12D1800RF, there is a delay of tCalDly and then the Poweron Calibration is executed. This is why it is recommended to set the CalDly Pin via an external pull-up or pull-down resistor. This ensured that the state of that input will be properly set at the same time that power is applied to the ADC and tCalDly will be a known quantity.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 www.ti.com FPGA writes Control Pins Power to ADC ADC output valid CalDly Calibration Power-on Calibration On-command Calibration Figure 6-13. Power-on with Control Pins set by FPGA pre Power-on Cal FPGA writes Control Pins Power to ADC CalDly Calibration Power-on Calibration On-command Calibration Figure 6-14. Power-on with Control Pins set by FPGA post Power-on Cal 6.4.6.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 mV www.ti.com Slope = 1.22V/ms 1900 1710 VA 1490 1210 660 635 520 DCLK 300 time Figure 6-15. Supply and DCLK Ramping 6.4.7 RECOMMENDED SYSTEM CHIPS TI recommends these other chips including temperature sensors, clocking devices, and amplifiers in order to support the ADC12D1800RF in a system design. 6.4.7.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 www.ti.com In the following typical application, the LM95213 is used to monitor the temperature of an ADC12D1800RF as well as an FPGA, see Figure 6-16. If this feature is unused, the Tdiode+/- pins may be left floating. 7 ADC12D1XXX IE = IF D1+ 100 pF IR 5 IE = IF FPGA D- 100 pF 6 D2+ IR LM95213 Figure 6-16. Typical Temperature Sensor Application 6.4.7.
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ADC12D1800RF www.ti.com 6.5 SNAS518I – JULY 2011 – REVISED JANUARY 2014 Register Definitions Twelve read / write registers provide several control and configuration options in the Extended Control Mode. These registers have no effect when the device is in the Non-extended Control Mode. Each register description below also shows the Power-On Reset (POR) state of each control bit. See Table 6-14 for a summary.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 www.ti.com Bit 11 PDI: Power-down I-channel. When this bit is set to 0b, the I-channel is fully operational; when it is set to 1b, the I-channel is powered-down. The I-channel may be powered-down via this bit or the PDI Pin, which is active, even in ECM. Bit 10 PDQ: Power-down Q-channel. When this bit is set to 0b, the Q-channel is fully operational; when it is set to 1b, the Q-channel is powered-down.
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ADC12D1800RF www.ti.com SNAS518I – JULY 2011 – REVISED JANUARY 2014 Table 6-18. I-channel Full Scale Range Adjust Addr: 3h (0011b) Bit 15 Name Res POR 0 POR state: 4000h 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 FM(14:0) 1 0 0 0 0 0 0 0 Bit 15 Reserved. Must be set to 0b. Bits 14:0 FM(14:0): FSR Magnitude. These bits increase the ADC full-scale range magnitude (straight binary coding.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 www.ti.com Table 6-21. Bias Adjust Addr: 6h (0110b) Bit POR state: 1C2Eh 15 14 13 12 11 10 9 Name 8 7 6 5 4 3 2 1 0 0 1 0 1 1 1 0 MPA(15:0) POR 0 Bits 15:0 0 0 1 1 1 0 0 0 MPA(15:0): Max Power Adjust. This register must be written to 1C0Eh to achieve full rated performance for Fclk > 1.6GHz. Table 6-22.
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ADC12D1800RF www.ti.com SNAS518I – JULY 2011 – REVISED JANUARY 2014 Table 6-26. Q-channel Full-Scale Range Adjust Addr: Bh (1011b) Bit 15 Name Res POR 0 POR state: 4000h 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 FM(14:0) 1 0 0 0 0 0 0 0 Bit 15 Reserved. Must be set to 0b. Bits 14:0 FM(14:0): FSR Magnitude. These bits increase the ADC full-scale range magnitude (straight binary coding.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 www.ti.com Table 6-28. Aperture Delay Fine Adjust (1) Addr: Dh (1101b) Bit 15 POR state: 0000h 14 Name 12 11 10 9 FAM(5:0) POR (1) 13 0 0 0 0 8 7 6 5 4 Res 0 0 0 3 2 1 0 0 0 0 0 Res 0 0 0 0 0 This feature functionality is not tested in production test; performance is tested in the specified / default mode only.
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ADC12D1800RF www.ti.com SNAS518I – JULY 2011 – REVISED JANUARY 2014 Table 6-30. Reserved Addr: Fh (1111b) Bit 15 POR state: 001Dh 14 13 12 11 10 9 8 Name POR Bits 15:0 7 6 5 4 3 2 1 0 0 0 0 1 1 1 0 1 Res 0 0 0 0 0 0 0 0 Reserved. This address is read only.
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ADC12D1800RF SNAS518I – JULY 2011 – REVISED JANUARY 2014 www.ti.com Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (APRIL 2013) to Revision I • Page Added notification that Aperture Delay Adjust feature cannot be used in DES mode (DESI, DESQ, DESIQ or DESCLKIQ) for CLK frequencies above 1600 MHz in multiple places where applicable. ................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 7-Mar-2015 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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MECHANICAL DATA NXA0292A www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.