ASD8P-MT1 Series M-2 PCIe x2 Gen2 SSD Module Specification Revision: 1.00 Revision Date: August 5, 2014 Part No: 50-1Z171-2010 Advance Technologies; Automate the World.
Revision History Revision 1.
Copyright 2014 ADLINK Technology, Inc. Disclaimer The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.
Table of Contents 1 2 Overview ..................................................................................... 5 Product Specification ................................................................ 6 2. 1 2. 2 2. 3 2. 4 2. 5 Functional Block Diagram........................................................................... 16 Mechanical Drawing: .................................................................................. 16 Architecture ......................................................
1 Overview The ASD8P-MT1 Series PCIe x2 Gen2 Solid State Drive (SSD) delivers leading performance in an industry standard M. 2 2280-D5-B-M form factor, while simultaneously improving system responsiveness over standard rotating drive media. By combining leading NAND flash memory technology with our innovative high performance firmware, ADLINK delivers an SSD for PCIe hard disk drive drop-in replacement with enhanced performance, reliability, ruggedness and power savings.
2 Product Specification Form Factor: M. 2 type 2280-D5-B-M SSD form factor Capacity: M. 2 2280-D5-B-M 128GB (ASD8P-MT1128-CT) M. 2 2280-D5-B-M 256GB (ASD8P-MT1256-CT) M. 2 2280-D5-B-M 512GB (ASD8P-MT1512-CT) Table 1. User Addressable Sectors Unformatted capacity Total user addressable sectors in LBA mode 128GB 250,069,680 256GB 500,118,192 512GB 1,000,215,216 Notes: 1. 1GB = 1,000,000,000 bytes, not all of the memory can be used for storage. 2.
Bandwidth Performance Table 2. Maximum Sustained Read and Write Bandwidth on Windows 7 x64 platform Capacity 128 GB 256 GB 512 GB Access Type MB/s Sequential Read Sequential Write Sequential Read Sequential Write Sequential Read Sequential Write Up to 750 (PCIe Gen2) Up to 320 (PCIe Gen2) Up to 740 (PCIe Gen2) Up to 570 (PCIe Gen2) Up to 740 (PCIe Gen2) Up to 610 (PCIe Gen2) Table 3.
128GB 256GB 512GB 4K Read (IOPS) 94,000 (PCIe Gen2) 4K Write (IOPS) 78,000 (PCIe Gen2) CDM QD32 IOPS up to Read 95,000 , Write 83,000 4K Read (IOPS) 96,000 (PCIe Gen2) 4K Write (IOPS) 94,000 (PCIe Gen2) CDM QD32 IOPS up to Read 100,000 , Write 100,000 4K Read (IOPS) 98,000 (PCIe Gen2) 4K Write (IOPS) 92,000 (PCIe Gen2) CDM QD32 IOPS up to Read 100,000 , Write 100,000 Notes: 1) Performance measured using IOMETER with queue depth set to 32, Crystal Disk Mark QD32.
Windows 7 x86, x64; Windows 8 x86, x64; Linux series, Red Hat 6. 5, Fedora, SUSE, Ubuntu; Windows Server 2008, 2012 Chipsets Please make sure the BIOS of the motherboard is updated to the latest version.
Manufacturer Platform ASUS Dell Dell Dell Dell M5A99X EVO 519 546 MT 580 DT 625 Dell Dell Dell Dell Dell Dell Dell Dell Dell Dell Dell Dell Dell Dell Dell Dell Dell Chipset AMD 990 AMD RS780 AMD RS780 AMD RS880 AMDRD780 /AMD HAMMER DDR2 IMC 230 Intel® 82801GBICH7 XE Intel® 82801JDO ICH10DO T3500 Intel® 82801JR ICH10R T7500 Intel® 82801JR ICH10R T5500 Intel® 82801JR ICH10R Aurora Intel® 82801JRICH10 R Area 51 Intel® 82801JRICH10 R R5500 Intel® 82801JRICH10 R 9200 (XPS 410) Intel® 945P 420 Intel® X3
Manufacturer Platform Chipset Manufacturer Platform Chipset Dell Dell Dell Dell Dell Dell Dell Dell Dell Dell 540s) 220 580s 460 MT 580 980 980 DT 980 MT T1700 3020 9020 Intel® G45 Intel® H57 Intel® H67 Intel® H57 Intel® Q57 Intel® Q57 Intel® Q57 Intel® C226 Intel® H81 Intel® HM87 Lenovo Lenovo Lenovo Lenovo Lenovo Lenovo Lenovo Lenovo Lenovo Lenovo Intel® H57 Intel® H61 Intel® Q35 Intel® Q35 Intel® Q41 Intel® Q57 Intel® Q65 Intel® Q67 Intel® X38 Intel® X58 Dell XE2 Intel® Q87 Gigabyte Dell D
Manufacturer Platform Chipset Manufacturer Dell Dell 3010 DT CM6650 Intel® H61 Intel® H67 ASRock ASRock Dell Dell Dell 8500 760 DT 960 DT Intel® H77 Intel® Q43 Intel® Q45 ASRock ASRock ASRock Dell 790 DT Intel® Q65 ASRock Dell 990 DT Intel® Q67 ECS Dell Dell Dell 7010 MT 9010 DT 745 MT Intel® Q77 Intel® Q77 Intel® Q965 ECS ECS ECS Platform KILLER Z87 Pro3 Fatal1ty H87 Performance B85M Pro4 H81M-DGS 970 Extreme3 990FX Extreme3 Z87H3-A2X Extreme H87H3-M3 B85H3-M3 H81H3-M4 Chipset Inte
Certifications Table 7. Device Certifications Certification CE compliant UL certified Description Indicates conformity with the essential health and safety requirements set out in European Directives Low voltage Directive and EMC Directive Underwriters Laboratories, Inc.
Reliability Table 10. Reliability specifications Parameter Mean Time between Failure (MTBF) Value > 1,500,000 hours Power on/off cycles 50000 cycles Notes: 1) MTBF is calculated based on a Part Stress Analysis. It assumes nominal voltage. With all other parameters within specified range. 2) Power on/off cycles is defined as power being removed from the drive, and the restored. Most host systems remove power from the drive when entering suspend and hibernate as well as on a system shutdown.
Test Description Performance criteria Reference standard Radiated RF immunity 80~1000MHz, 3V/m, 80% AM with 1 KHz sine 900 MHz, 3 V/m, 50% pulse modulation at 200Hz A IEC 61000-4-3: 2008 ±1KV on AC mains ±0. Electrical fast transient 5KV on external I/O ±1KV differential ±2KV common, AC mains 150KHz~80 MHz, 3 Conducted RF immunity Vrms, 80% AM with 1KHz sine Surge immunity Power frequency magnetic field 50Hz, 1A/m (r. m. s. ) B B IEC 61000-4-4: 2004 +Corr. 1: 2006 +Corr.
2.1 Functional Block Diagram DDR3 DRAM PCIe Interface 2.2 Flash Memory Controller NAND Flash Array Mechanical Drawing: M.
2.3 Architecture The ASD8P-MT1 PCIe Gen2 x 2 Lane Solid State Drive (SSD) utilizes a cost effective system-onchip (SoC) design to provide a full 1GB/s bandwidth with the host while managing multiple flash memory devices on multiple channels internally. 2.4 Power Mode Support PCI Express feature enables the hardware to engage actively in automatic Link power management. ASD8P-MT1 PCIe Gen2 x 2 Lane SSD Supports L0, L0s and L1 mode.
2.5 Bootable Device: The ASD8P-MT1 PCIe Gen2 x 2 Lane Solid State Drive (SSD) is configured as a bootable device. This supported function allows users to manage it as a main system drive and to boot from PCIe SSD.
3 Pin Locations and Signal Descriptions 3.1 Pin Locations The data and power connector pin locations of the ASD8P-MT1 PCIe SSD Gen2 x 2 Lane are shown below. This M. 2 device contains Socket 2 + B-M key. 3.2 M. 2 Socket Definition The PCI Express interface supported in Socket 3 is a 4 Lane PCI Express interface intended for premium SSD devices that need this sort of host interface.
3.3 Socket 2 PCIe-based SSD Module Pinout Pin#38 is reserved for obeying PCI Express specification; Devslp is supported by ASD8P-MT1.
4 PCI Express 4.1 Interface The PCI Express interface supports the x1 PCI Express interface (one Lane). A Lane consists of an input and an output high-speed differential pair. Also supported is a PCI Express reference clock. Refer to the PCI Express Base Specification for more details on the functional requirements for the PCI Express interface signals. Socket 1 pin out has provisions for an additional PCI Express lane indicated by the suffix 1 to the signal names.
CLKREQ# Signal The CLKREQ# signal is an open drain, active low signal that is driven low by the PCI Express M. 2 add-I Card function to request that the PCI Express reference clock be available (active clock state) in order to allow the PCI Express interface to send/receive data. Operation of the CLKREQ# signal is determined by the state of the Enable Clock Power Management bit in the Link Control Register (offset 010h).
Additionally, the device must ensure that it does not pull CLKREQ# low unless CLKREQ# is being intentionally asserted in all cases; including when the related function is in D3cold. This means that any component implementing CLKREQ# must be designed such that: Unpowered CLKREQ# output circuits are not damaged if a voltage is applied to them from other powered “wire-ORed” sources of CLKREQ#.
To exit L1, the device must assert CLKREQ# (low) to re-enable the reference clock. After the device asserts CLKREQ# (low) it must allow that the reference clock will continue to be in the parked clock state for a delay (TCRLon) before transitioning to the active clock state. The time that it takes for the device to assert CLKREQ# and for the system to return the reference clock to the active clock state are serialized with respect to the remainder of L1 recovery.
Refer to the PCI Express Card Electromechanical Specification for more details on the functional requirements for the PERST# signal. WAKE# Signal PCI Express M. 2 Cards must implement WAKE# if the card supports either the wakeup function or the OBFF mechanism. Refer to the PCI Express Card Electromechanical Specification for more details on the functional requirements for the WAKE# signal. 4.4 SDIO Interface The M.
4.5 UART Interface The on-chip asynchronous interface (UART, Universal Asynchronous Receiver and Transmitter) can be used for communication with other host controllers or systems. The UART can handle 8-bit data frames and inserts one start and one stop bit (with/without parity). The format of the UART frame.
5 ATA Command Sets 5.1 ATA Command The ASD8P-MT1 PCIe Gen2 x 2 Lane SSD supports all the mandatory ATA commands defined in the ATA/ATAPI-8 specification.
Table 13 Supported ATA Command Set Command Name Command Code Command Name Command Code DATA SET MANAGEMENT 06h SET MULTIPLE MODE C6h READ SECTOR(S) 20h READ DMA C8h READ SECTOR(S) EXT 24h WRITE DMA CAh READ DMA EXT 25h WRITE MULTIPLE FUA EXT CEh READ NATIVE MAX ADDRESS EXT 27h STANDBY IMMEDIATE E0h READ MULTIPLE EXT 29h IDLE IMMEDIATE E1h READ LOG EXT 2Fh STANDBY E2h WRITE SECTOR(S) 30h IDLE E3h WRITE SECTOR(S) EXT 34h READ BUFFER E4h WRITE DMA EXT 35h CHECK POWER M
Identify Device Data The following table details the sector data returned after issuing an IDENTIFY DEVICE command.
F=Fixed Word V=Variable 128GB X=Both 256GB 512GB Default Value Description 63 V 0007h 0007h 0007h 0007h Multi-word DMA modes supported/selected 64 F 0003h 0003h 0003h 0003h PIO modes supported 65 F 0078h 0078h 0078h 0078h 66 F 0078h 0078h 0078h 0078h 67 F 0078h 0078h 0078h 0078h 68 F 0078h 0078h 0078h 0078h 69-70 F 0000h 0000h 0000h 0000h 71-74 F 0000h 0000h 0000h 0000h 75 F 001Fh 001Fh 001Fh 001Fh 4: 0 Maximum Queue depth-1=31 76 V 070Eh 070E
F=Fixed Word V=Variable 128GB X=Both 256GB 512GB Default Value Description 96 F 0000h 0000h 0000h 0000h Streaming Transfer Time . DMA 97 F 0000h 0000h 0000h 0000h Streaming Access Latency .
F=Fixed Word V=Variable 128GB X=Both 209 256GB 512GB Default Value Description Alignment of logical blocks within a physical block Write-Read-Verify Sector Count Mode 3 (DWord) Write-Read-Verify Sector Count Mode 2 (DWord) F 4000h 4000h 4000h 4000h F 0000h 0000h 0000h 0000h F 0000h 0000h 0000h 0000h 214 F 0000h 0000h 0000h 0000h NV Cache Capabilities 215216 F 0000h 0000h 0000h 0000h NV Cache Size in Logical Blocks (DWord) 217 F 0001h 0001h 0001h 0001h Nominal media ro
5.2 Power Management Command Set The ASD8P-MT1 PCIe Gen2 x 2 Lane SSD supports the power management command set, which consists of - CHECK POWER MODE - IDLE - IDLE IMMEDIATE - SLEEP - STANDBY - STANDBY IMMEDIATE 5.3 Security Mode Feature Set The ASD8P-MT1 PCIe Gen2 x 2 Lane SSD supports the Security Mode Feature Set, which provide high reliability of data storage. Implementing personal password for disk drive to prevent unauthorized access is available with this Security Mode Feature Set .
- SECURITY FREEZE LOCK The drive can be secured by executing SECURITY FREEZE LOCK command- After command completion, the drive will be set to Frozen mode to prevents changes to all Security states and any other commands to it will be aborted- The Frozen mode can be disabled by power-off or rebooting- 5.
Thresholds from the Attribute Threshold sectors and then waits for the host to transfer the 512 bytes of Attribute Thresholds information from the device. SMART ENABLE/DISABLE ATTRIBUTE AUTOSAVE (Code D2h) This subcommand enables and disables the attribute auto save feature of the device.
SMART READ LOG SECTOR (Code D5h) This command returns the indicated log sector contents to the host. Sector count sepcifies the number of sectors to be read from the specified log. The log transfferred by the drive shall start at the first sector in the speicified log, regardless of the sector count requested. SMART READ LOG SECTOR (Code D6h) This command writes 512 bytes of data to the specified log sector. The 512 bytes of data are transferred at a command and the LBA Low value shall be set to one.
SMART READ LOG SECTOR (Code DAh) This subcommand is used to communicate the reliability status of the device to the host's request. Upon receipt of the SMART Return Status subcommand the device asserts BSY, saves any updated Attribute Values to the reserved sector, and compares the updated Attribute Values to the Attribute Thresholds.
Subcommand EXECUTE OFF-LINE IMMEDIATE 5.
5.6 48-Bit Address Command Set The ASD8P-MT1 PCIe Gen2 x 2 Lane SSD supports the Host Protected Area command set, which consists of: - FLUSH CACHE EXT - READ DMA EXT - READ NATIVE MAX ADDRESS EXT - READ SECTOR(S) EXT - READ VERIFY SECTOR(S) EXT - READ MULTIPLE EXT - SET MAX ADDRESS EXT - WRITE DMA EXT - WRITE MULTIPLE EXT - WRITE MULTIPLE FUA EXT - WRITE SECTOR(S) EXT 5.
6 SATA Command Sets 6.1 SATA Command The SATA 3. 0 Specification is a super set of the ATA/ATAPI-8 specification with regard to supported commands. The ASD8P-MT1 PCIe Gen2 x 2 Lane SSD also supports the following features which are unique to the SATA 3. 0 Specification. Software Settings Preservation The ASD8P-MT1 PCIe Gen2 x 2 Lane SSD supports the SET FEATURES parameter to enable/disable the preservation of software settings.
7 References This document references standards defined by a variety of organizations as listed below. Table 16 Standards References Date Title Location Dec 2008 VCCI http: //www. vcci. or. jp/vcci_e/general/join/index. html July 2007 ROHS Search for material description datasheet at http: //intel. pcnalert. com July 2007 SFF-8144, 1. 8” drive form factor http: //www. sffcommittee. org February 2007 Serial ATA Revision 2. 6 http: //www. sata-io. org May 2006 SFF-8223, 2.
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