PRELIMINARY Am79C930 PCnet™-Mobile Single-Chip Wireless LAN Media Access Controller DISTINCTIVE CHARACTERISTICS ■ Capable of supporting the IEEE 802.11 standard (draft) ■ Supports the Xircom Netwave™ media access control (MAC) protocols ■ Supports MAC layer functions ■ Individual 8-byte transmit and 15-byte receive FIFOs ■ Integrated intelligent 80188 processor for MAC layer functions ■ Glueless PCMCIA bus interface conforming to PC Card standard—Feb.
P R E L I M I N A R Y ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed by a combination of the elements below.
P R E L I M I N A R Y BLOCK DIAGRAM PCMCIA Mode JTAG Control Block MOE TRST TMS/T3 TDI/T1 TDO/T2 MWE MA 16–0 MD 7–0 RXCIN ANTSLT XCE ANTSLT SCE SAR6–0 FCE ADIN2–1 ADREF RXDATA RXC USER6–0 SDCLK A14–0 Transceiver Attachment Interface D7–0 SDDATA SDSEL3–1 REG CA16–8 CE1 CAD 7–0 DRQ0 TXCMD OE INT1 DRQ1 TXMOD IORD IOWR RESET WE WAIT Bus Interface Unit (PCMCIA) ALE MAC Control Unit (80188 core) INT0 TXCMD TXDATA TXDATA RXPE WR TXPE SRDY HFPE HFCLK INPACK IREQ UCS STSCHG LC
P R E L I M I N A R Y BLOCK DIAGRAM Bus Interface Unit MD[7:0] IREQ A14–0 or LA23–17, SA16–0 D7–0 MA[16:0] System Interrupt Generator Address Buffer Data Buffer CA16 Latch CA15–8 Bus Multiplexer CAD7–0 MIR0 MIR1 ... MIR15 SIR0 SIR1 ...
P R E L I M I N A R Y BLOCK DIAGRAM Transceiver Attachment Interface Unit IRQ Interrupt Generator Transceiver Control Signals Transceiver Interface Unit Control MD[7:0] TIR0 TIR... TIR31 TCR0 TCR...
AMD PRELIMINARY TABLE OF CONTENTS DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 BLOCK DIAGRAM . . . . . . . . . . . . .
PRELIMINARY AMD Pin 3: USER4/LA17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Pin 45: STSCHG/BALE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Pin 90: USER0/RFRSH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Pin 91: USER1/IRQ12/EXTCTS/EXINT188 . . . . . . . . . . . . . . . . . . . . . .
AMD PRELIMINARY Bus Interface Unit Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Transceiver Attachment Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 TX FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 TX Power Ramp Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PRELIMINARY AMD LED Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 RESET Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 SWRESET (SIR0[7]) . . . . . . . . . . . . . . . .
AMD PRELIMINARY TIR10: TX FIFO Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 TIR11: Transmit Sequence Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 TIR12: Byte Count Register LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 TIR13: Byte Count Register MSB . . . . . . . . . . . . . . . . . . . . . . . .
PRELIMINARY AMD TCR24: RSSI Sample Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 TCR25: RSSI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 TCR26: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 TCR27: TIP LED Scramble . . . . . . . . . . . . . . . . . . . . . . .
AMD PRELIMINARY TIMING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 PCMCIA Bus Interface Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 ISA Bus Interface Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Memory Bus Interface Waveforms . . . . . . . . . . . . . . . .
P R E L I M I N A R Y 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 LLOCKE TXDATA TXCMD ANTSLT VDDU2 VDD5 AVDD ADREF AVSS ADIN2 ADIN1 PWRDWN ANTSLT TXMOD VSST TXPE FDET VSS TXCMD VDDT RXCIN RXSDATA RXPE TXDATA HFPE HFCLK LFPE LFCLK VSST TXC SAR6 SAR5 SAR4 SAR3 SAR2 SAR1 PCMCIA CONNECTION DIAGRAM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Am79C930 108
P R E L I M I N A R Y PCMCIA PIN SUMMARY Listed by Pin Number Pin No. 14 Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.
P R E L I M I N A R Y PCMCIA PIN LIST Listed by Pin Name Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.
P R E L I M I N A R Y PCMCIA PIN FUNCTION SUMMARY PCMCIA Pin Summary No.
P R E L I M I N A R Y PCMCIA PIN FUNCTION SUMMARY (continued) PCMCIA Pin Summary (continued) No. of Pins Pin Name Pin Function Pin Style 1 TDO Test Data Out—this is the data output signal for IEEE 1149.1 testing 1 TMS Test Mode Select—this is the test mode select for IEEE 1149.1 testing I 1 TRST Test Reset—this is the reset signal for IEEE 1149.
P R E L I M I N A R Y PCMCIA PIN FUNCTION SUMMARY (continued) PCMCIA Pin Summary (continued) No.
P R E L I M I N A R Y ISA PLUG AND PLAY BLOCK DIAGRAM TRST JTAG Control Block MOE TMS/T3 TDI/T1 TDO/T2 MWE MA 16–0 MD 7–0 RXCIN ANTSLT XCE ANTSLT SCE SAR6–0 FCE ADIN2–1 ADREF RXDATA RXC LA23–17 SDCLK SA126–0 IEEE 802.11 Network Interface Unit SD7–0 AEN CA16–18 BALE CAD 7–0 MEMR IOR Bus Interface Unit (ISA Plug and Play) INT1 ALE IOW RESET MEMW IOCHRDY IEEE 802.
P R E L I M I N A R Y 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 SA15 LA20 LA21 LA23 VDDU2 VDD5 AVDD ADREF AVSS ADIN2 ADIN1 PWRDWN ANTSLT TXMOD VSST TXPE FDET VSS TXCMD VDDT RXCIN RXSDATA RXPE TXDATA HFPE HFCLK LFPE LFCLK VSST TXC SAR6 SAR5 SAR4 SAR3 SAR2 SAR1 ISA PLUG AND PLAY CONNECTION DIAGRAM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Am79C930
P R E L I M I N A R Y ISA PLUG AND PLAY PIN LIST Listed by Pin Number Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.
P R E L I M I N A R Y ISA PLUG AND PLAY PIN LIST Listed by Pin Name Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.
P R E L I M I N A R Y ISA PLUG AND PLAY PIN SUMMARY No.
P R E L I M I N A R Y ISA PLUG AND PLAY PIN SUMMARY (continued) No.
PRELIMINARY PIN DESCRIPTIONS Pins with Internal Pull Up or Pull Down Devices Several pins of the Am79C930 device include internal pull up or pull down devices. With the exception of the RESET pin, these pins are fully programmable as inputs or outputs when the PCMCIA mode has been selected. A subset of these pins is programmable when the ISA Plug and Play mode has been selected.
AMD PRELIMINARY The functionality of the following pins is determined, at least in part, by the connection of the PCMCIA pin: Data Bus ISA Plug and Play Mode Pin Name USER6 USER6/IRQ5 OE USER5 USER5/IRQ4 Output Enable USER4 LA17 USER3 SA16 USER2 LA19 USER1 USER1/IRQ12 USER0 RFRSH A[14:0] SA[14:0] LLOCKE SA15 D[7:0] SD[7:0] CE1 LA18 OE MEMR WE MEMW REG AEN TXDATA LA20 TXCMD LA21 INPACK LA22 ANTSLT LA23 WAIT IOCHRDY STSCHG BALE IORD IOR IOWR IOW IREQ IRQ9 R
AMD PRELIMINARY REG CE1 Standby mode X H Common Memory Read Even Byte H L Common Memory Read Odd Byte H L H Function Mode IORD IOWR A0 OE WE X X X X X High-Z H H L L H Even Byte H H L H Odd Byte Even Byte D7–0 Common Memory Write Even Byte H L H H L H L Common Memory Write Odd Byte H L H H H H L Odd Byte Attribute Memory Read Even Byte L L H H L L H Even Byte Attribute Memory Read Odd Byte L L H H H L H Odd Byte Attribute Memory Write E
AMD PRELIMINARY IOR I/O Read Memory Interface Pins Input The IOR signal is made active by the ISA host in order to read data from the Am79C930 device’s I/O space. MA16–0 Memory Address Bus Output The IOW signal is made active by the ISA host in order to write data to the Am79C930 device’s I/O space. Signals MA0 through MA16 are address-bus-output lines which enable direct address of up to 128 Kbytes of SRAM memory and 128 Kbytes of Flash memory in a Am79C930-based application.
PRELIMINARY of TXC, allowing ample setup and hold time for valid sampling of TXDATA with the rising edge of TXC. Clock Pins CLKIN System Clock Input CLKIN is the clock input for the Am79C930 device’s logic functions. CLKIN is used to drive the CLKIN input of the embedded 80188 core. The BIU section uses the CLKOUT signal from the 80188 embedded core as a reference. The register interface portions of the TAI use the CLKIN signal as a reference.
AMD PRELIMINARY is deasserted when the RESET pin is issued or the CRC reset bit is set to 1 (SIR0); when the TXS bit is set to 1 (TIR8) or the RXS bit is set to 1 (TIR16); when TXRES bit set to 1 (TIR8), or the RXRES bit is set to 1 (TIR16), or the SRES bit is set to 1 (TIR0). PLL is used for clock recovery, then the RXDATA input will expect valid data at rising edges of the RXCIN input. External versus internal PLL use is determined through the setting of the ECLK bit in TCR2.
PRELIMINARY TXMOD Transmit Modulation Enable Output TXMOD is an active low output that is used to enable the transmit modulation function of the attached transceiver. This pin is directly controlled by the transmit state machine in the TAI and the TXMOD bit of TIR11. The timing of the TXMOD signal is programmable from a TAI register. The polarity of this pin is programmable from a TAI register.
AMD PRELIMINARY IEEE 1149.1 Test Access Port Pins TCK Test Clock Input TCK is the clock input for the boundary scan test mode operation. TCK frequency may be as high as 10 MHz. TCK does not have an internal pull-up resistor and must be connected to a valid TTL or CMOS level at all times. TCK must not be left unconnected. TDI Test Data Input Input TDI is the test data input path to the Am79C930 device. If left unconnected, this pin has a default value of HIGH. supply voltage.
PRELIMINARY AMD VSSP VCC VDDT, VDDU1, VDDU2, VDDP, VDDM AVDD, VDD5 Acceptable Combination 5V All at 5 V Both at 5 V Yes 3V All at 5 V Both at 5 V Yes 3V Any Combination of 3 V and 5 V Both at 5 V Yes 3V All at 3 V Both at 5 V Yes VDDM 5V All at 3 V Both at 5 V No Memory Interface Power (3 Pins) 5V Any Combination of 3 V and 5 V Both at 5 V No 5V All at 5 V Any Combination of 3 V and 5 V No There are three Memory Interface power supply pins.
AMD PRELIMINARY for an output function. This means that there are configurations for which a read of the pin data register bit will not reflect what has most recently been written to the pin data register bit ( i.e., if a pin is configured as an output with its data source as some internal circuit, then the user may write the pin data bit with a given value, and a read of this same bit will yield the output function value, which may not necessarily match the value just written to the data bit).
AMD PRELIMINARY Note that a read of the USERDT[0] bit (TIR29[0]) will always give the current USER0/RFRSH pin value, regardless of pin configuration setting.
AMD PRELIMINARY In addition to the functionality listed above, the RXC/ IRQ10/EXTA2DST pin may be used to control the start of the A/D conversion process. When the UXA2DST bit of TCR25 has been set to a 1, then the normal internal state machine control of the A/D sample and conversion procedure or a rising edge on the RXC/ IRQ10/EXTA2DST pin will trigger an A/D conversion procedure.
AMD PRELIMINARY ENXCHBSY bit of TCR28 and the CHBSYU bit of TIR5 and operates independently of the bits in the table below. In addition to the functionality listed above, the USER5/IRQ4/EXTCHBSY pin may be used as the source for CCA information, instead of relying on the internal CCA logic of the Am79C930 device. When using the external CCA information, CCA information from the internal logic will be unavailable.
AMD PRELIMINARY Pin 101: SDCLK The SDCLK pin may be configured for input or output operation. The output drive may be programmed for register-driven or auto-pulse generation. The auto-pulse may be programmed for either active low or active high SDCLK Pin Direction operation. SDCLK pin configuration is accomplished according to the following table: Note that a read of the SDC bit (TIR2[2]) will always give the current SDCLK pin value, regardless of pin configuration setting.
AMD PRELIMINARY Pin 115: TXC The TXC pin may be configured for input or output operation according to the table below: TXC input configuration is the reset default configuration. This configuration allows an external transceiver to control the clock that serves as the reference for the transmit data. While in this configuration, the internal TX state machine continues to operate with a reference clock derived from a divided version of the CLKIN input.
AMD PRELIMINARY Pin 126: TXCMD The TXCMD pin may be configured to drive a transceiver control reference signal, using one of two timing sources plus input from the TXCMD bit of TIR11 (TIR11[0]), according to the following table: RCEN TIR11[3] TXCMD Pin Direction 0 O O_TX 1 O TIR11[0] & T1 Transmit state machine generated signals T1, T2, T3, TXP_ON and O_TX have the timing indicated in the TXCMD Pin Value diagram in section Am79C930-Based TX Power Ramp Control.
AMD PRELIMINARY some functionality is only available in PCMCIA mode. Pin functionality is programmed according to the following table: Note that a read of the ANTSLTD bit (TCR7[1]) will always give the current ANTSLT/LA23 pin value without inversion, regardless of pin configuration setting.
AMD PRELIMINARY PCMCIA Pin Value LLOCKEN TCR14[6] LLOCKE/ SA15 Pin Direction LLOCKE/ SA15 Pin Value 0 X I NA 1 0 I NA 1 1 O TIR11[4] (SA15 input function) and TCR). These registers are controlled through 80188 firmware instructions. FUNCTIONAL DESCRIPTION Basic Functions System Bus Interface Function Detailed Functions The Am79C930 device is designed with a choice of two system bus interfaces.
PRELIMINARY AMD PCMCIA Interface — The Am79C930 device fully supports the PCMCIA standard, revision 2.1. CE1) are automatically translated into the appropriate memory interface signals (RD, WR). The PCMCIA interface on the Am79C930 device supports both memory and I/O cycles. The data bus is 8 bits in width. The address bus is 15 bits in width. Memory accesses are enabled by default at power up.
AMD PRELIMINARY ISA (IEEE P996) Plug and Play Interface — The Am79C930 device fully supports the ISA Plug and Play specification, revision 1.0a. The ISA Plug and Play interface on the Am79C930 device supports both memory and I/O cycles. The data bus is 8 bits in width. The total system space required by the Am79C930 device is 32 Kbytes and 16 bytes of I/O space.
PRELIMINARY Memory Interface The memory interface is provided to support direct connection of both a non-volatile memory (typically Flash memory) and an SRAM and an additional peripheral device. Separate chip enables for Flash, SRAM, and an extra peripheral device exist in the memory interface.
AMD PRELIMINARY the media is considered busy and the MAC should defer to the existing message. This function is implemented in hardware in the TAI Unit. Additionally, each station is required to implement a Net Allocation Vector (NAV) in order to determine when the medium is expected to be busy. The NAV is updated as Request-to-Send (RTS), Send (CTS), and DATA frames arrive at the station. RTS, CTS, and DATA frames include a field that indicates the expected length of the RTS-CTS-DATA-ACK exchange.
PRELIMINARY accesses to use the memory interface bus during the T1 and T2 cycles of the 80188 access. The Memory Address Bus is internally shared between the 80188 core and the BIU. This bus also attaches to the Transceiver Attachment Unit as an input only. Data values are delivered from the 80188 core to the SRAM through the BIU and then to the Memory Data Bus (signals MD[7:0]). This bus is shared by the BIU for access to the SRAM and also attaches to the Transceiver Attachment Unit.
AMD PRELIMINARY Transceiver Attachment Interface Unit selection of antennas. If automatic antenna selection is not used, then the desired antenna selection is accomplished through the setting of appropriate bits in one of the TIR registers.
AMD PRELIMINARY 4 X TSCLK TXS TGAP1 X TBCLK + 2 X TSCLK TGAP4 X TBCLK + 2 X TSCLK T1 TGAP2 X TBCLK + 2 X TSCLK TGAP3 X TBCLK + 2 X TSCLK T2 2 X TSCLK 2 X TSCLK T3 3 X TSCLK 7 X TSCLK O_TX DRB X TBCLK HDB X TBCLK TXP_ON 1st Data Bit TX default bit TXDATA Last Data Bit TX default bit TSCLK = TCLKIN when CLKGT20 = 0 TBCLK = TSCLK X 20 20183B-7 Figure 1.
AMD PRELIMINARY Transceiver-Based TX Power Ramp Control — The CTS signal may be used to synchronize operations between the Am79C930 device and transceivers that wish to perform their own transmit timing sequence. When the CTS signal is enabled by setting the CTSEN bit of TCR7 to a 1, then the CTS input acts as a gating signal with respect to the start of the Am79C930 transmit operations. An example of the use of the CTS signal would be when a transceiver is in control of the decision to transmit.
PRELIMINARY values were found to be correct. These register values can be used to determine the end of a received frame. When good CRC values are found, these may be signaled to the 80188 core through interrupt bits in TIR5. The CRC32 polynomial is X32+X26+X23+X22+X16 +X12+X11+X10+X8+X7+X5+X4+X2+X+1; the initial condition of the CRC32 calculation is FFFF FFFFh; and the final remainder of the CRC32 operation is DEBB 20E3h.
AMD PRELIMINARY register of TCR4. ADIN2 becomes active after ADIN1 by the amount of delay specified in the RSSI Sample Start time of TCR24. ADIN2 remains active for the time programmed in the A2DT register (TCR25). The converter output should be connected to the SAR pins, which act as inputs in this mode. External D/A mode allows the user to connect an external D/A converter to the Am79C930 device.
PRELIMINARY resolution is equal to twice the CLKIN period when the CLKGT20 bit of MIR9 is set to 1. (For a 1 MB data rate with CLKIN = 20 MHz and CLKGT20 = 0, resolution is 50 ns.) After each pair of rising edges is detected, the value of the rising edge separation counter is compared against the Baud Detect upper limit register value (TCR17) and also against the Baud Detect lower limit register value (TCR18). If the rising edge counter value is between these limits, then a GOOD counter is incremented.
AMD PRELIMINARY UBDCS TCR28:1 URSSI TCR28:0 Baud Detect Carrier Sense Decision RSSI >= RSSI Lower Limit CCA Result (CHBSY Bit of TIR26) 0 0 0 1 1 1 1 1 1 0 1 1 0 0 1 1 1 1 don’t care don’t care don’t care TRUE FALSE TRUE TRUE FALSE FALSE don’t care yes no don’t care don’t care yes no yes no CHBSY = TRUE CHBSY = TRUE CHBSY = FALSE CHBSY = TRUE CHBSY = FALSE CHBSY = TRUE CHBSY = FALSE CHBSY = FALSE CHBSY = FALSE The current CCA result is reported in the CHBSY bit of TIR26.
AMD PRELIMINARY Diversity decision logic for determining if a satisfactory antenna has been found. These inputs to the Stop Diversity decision logic are enabled by specific bits of TCR28. The UBDSD bit of TCR28 is used to select/ deselect the Baud Determination of Stop Diversity for use in Stop Diversity decisions and the URSSI bit of TCR28 is used to select/deselect RSSI information in Stop Diversity decisions.
AMD PRELIMINARY The following is a brief summary of the IEEE 1149.1 compatible test functions implemented in the Am79C930 device: Boundary Scan Circuit The boundary scan test circuit uses five pins: TRST, TCK, TMS, TDI, and TDO. These five pins are collectively labeled the TAP. The boundary scan test circuit includes a finite state machine (FSM), an instruction register, and a data register array. Internal pull-up resistors are provided for the TDI and TMS pins. The TCK pin must not be left unconnected.
PRELIMINARY mode, the host requests a power down by writing to the Power Down bit (bit 2) of the PCMCIA Card Configuration and Status Register. In the ISA Plug and Play mode, the host requests a power down by writing to the ISA Power Down bit, bit 7 of SIR3. In either case, the power down request will generate an interrupt to the 80188 embedded core.
AMD PRELIMINARY Writing a 1 to the Power Down bit of the ISA Power Down bit of SIR3 will cause a request for a power down to be generated to the 80188 core via an interrupt bit in MIR0. The decision to power down will be made by the 80188 controller, and the actual power down command will be executed by the 80188 controller by shutting off the transceiver and any other resources and then writing to the power down command bit (PDC) of MIR0.
AMD PRELIMINARY Am79C930 Device PCMCIA Mode Resource Requirements Common Memory Range Common Memory Size I/O Range I/O Size 0000h – 7FFFh 32 Kbytes OR 0 bytes 0000h – 0027h OR 0000h – 000Fh 40 OR 16 bytes The I/O range is adjusted through bit 2 (EIOW = Expand I/O Window) of SIR1 = Bank Switching Select register).
AMD PRELIMINARY Some of the Am79C930 device’s PCMCIA Common Memory locations have predefined uses and, therefore, are not freely available to the device driver.
AMD PRELIMINARY The SRAM is intended to serve as a shared memory resource between the driver operating through the system interface and the 80188 core operating through the Am79C930 memory interface bus. Even though SRAM memory locations 0 0400h through 0 043Fh are accessible from the system interface, these locations cannot be used for driver-firmware shared memory functions, since they are inaccessible from the 80188 core.
AMD PRELIMINARY Am79C930 Device PCMCIA Mode Attribute Memory Restricted Space PCMCIA Address in Attribute Memory SIR1[5:3] Size of Restricted Space 7FE0h – 7FFFh 111 32 bytes of Attribute memory, 16 bytes of actual Flash memory space PCMCIA I/O Resources — The Am79C930 device occupies either 16 or 40 bytes of I/O space, depending upon the setting of the EIOW bit (bit 2 of the BSS register (SIR1)).
AMD PRELIMINARY The following table indicates the mapping of all I/O resources that are accessible through the Am79C930 PCMCIA system interface.
AMD PRELIMINARY Am79C930 Device ISA Plug And Play Mode Memory And I/O Resource Requirements Memory Range Memory Size I/O Range I/O Size MBA*+0000h – MBA*+7FFFh 32 Kbytes OR 0 bytes IOBA**+0000h – IOBA**+000Fh and I/O 0279h and I/O 0A79h and I/O 0203h – I/O 03FFh (one byte only) 16 bytes *MBA = ISA Plug and Play Memory Base Address **IOBA = ISA Plug and Play I/O Base Address Note that since the Am79C930 device’s memory mapped resources are all accessible through the Local Memory Address Register a
PRELIMINARY address needs to be aligned to a 32K boundary in memory space. This alignment requirement should be included in the Resource Data that is programmed into the Flash device and read by the Plug and Play configuration utility. These conditions must be satisfied, since the Am79C930 device’s Bus Interface Unit will only use the upper 9 bits of the ISA memory address to determine when an address match has been achieved.
AMD PRELIMINARY The SRAM is intended to serve as a shared memory resource between the driver operating through the system interface and the 80188 core operating through the Am79C930 memory interface bus. Even though SRAM memory locations 0 0400h through 0 043Fh are accessible from the system interface, these locations cannot be used for driver-firmware shared memory functions, since they are inaccessible from the 80188 core.
AMD PRELIMINARY Am79C930 Device ISA Plug And Play Mode I/O MAP SIR1 Bits [2:0] Resource Size Physical Location of Resource Resource Name Mnemonic ISA I/O address SIR0: General Configuration Register SIR0: GCR IOBA*+0000h XXX** 1 byte BIU SIR1: Bank Switching Select Register SIR1: BSS IOBA+0001h XXX 1 byte BIU SIR2: Local Memory Address [7:0] SIR2: LMAL IOBA+0002h XXX 1 byte BIU SIR3: Local Memory Address [14:8] SIR3: LMAU IOBA+0003h XXX 1 byte BIU SIR4: I/O Data Port [7:0] SI
AMD PRELIMINARY ISA Plug and Play Register Set — The Am79C930 device fully supports the ISA Plug and Play specification, revision 1.0a. The Am79C930 device supports the Plug and Play Auto-configuration scheme.
AMD PRELIMINARY Am79C930 Device ISA Plug And Play Mode Plug And Play Register Set ISA Plug and Play Register Name Plug and Play Port ADDRESS Physical Location Set READ_DATA port 00h BIU Serial Isolation 01h BIU Configuration Control 02h BIU Wake [CSN] 03h BIU Resource Data 04h Flash Memory 1 FC00h–1 FFF0h Total of 1K–16 bytes.
AMD PRELIMINARY The Am79C930 device maps the Resource Data register accesses into 1K–16 of the upper 1 Kbytes of the Flash memory space so that Resource Data may be read from the Flash memory. Byte 0 of the Am79C930 device’s Resource Data is mapped to location 1 FC00h of the Flash memory. A maximum of 1K–16 bytes of Resource Data is allowed by the Am79C930 design.
AMD PRELIMINARY 80188 Core Memory Map Using Scheme “A”, LMCS=1FF8h, UMCS=E038h, MIR0[6]=0 80188 Address in Memory Active 80188 Chip Select Active Am79C930 Chip Select Size of Space Physical Location of Memory 0 0000h–0 03FFh LCS SCE 1 Kbytes SRAM Memory 0 0000h–0 03FFh 0 0400h–0 041Fh LCS none 32 bytes TIR 0–31 0 0420h–0 042Fh LCS none 16 bytes MIR 0–15 0 0430h–0 043Fh LCS XCE 16 bytes XCE locations 0–15 0 0440h–0 047Fh LCS none 64 bytes Reserved for future use–access to these
AMD PRELIMINARY MAC (80188 core) Memory Resources Restrictions — Some of the Am79C930 device 80188 core’s memory locations have predefined uses and, therefore, are not freely available to the firmware.
PRELIMINARY AMD All TIR registers. to TIR10. It is also possible to use 80188 MOV instructions to unload RX data from the RX FIFO. The RX FIFO may be unloaded by reading from TIR18. All TCR registers. DMA Channel Allocation In The 80188 Core All TAI state machines. 80188 DMA Channel DMA Request Source All PCMCIA registers. DRQ0 TAI RX FIFO NOT EMPTY All ISA PnP registers. DRQ1 TAI TX FIFO NOT FULL The ISA PnP state machine is returned to its idle state.
AMD PRELIMINARY The sleep state machine is returned to its idle state (i.e., awake). The memory bus arbitration state machine is returned to its idle state. The following registers and state machines which are UNAFFECTED by assertion of the SWRESET bit of SIR0[7]: SIR0[7] and all of SIR2[7:0] and SIR3[6:0] are unaffected by SWRESET. standalone 80188 controller having its RESET pin asserted.
AMD PRELIMINARY The sleep state machine is returned to its idle state (i.e., awake). The following registers and state machines are UNAFFECTED by assertion of the PCMCIA COR SRESET bit of COR[7]: SRES (TIR0[5]) The SRES bit of TIR0[5] can be used to reset the TAI section of the Am79C930 device. When the SRES bit is asserted, then the TAI section of the Am79C930 will be reset. All TCR registers are unaffected by COR SRESET.
AMD PRELIMINARY The MIR space contains 16 registers which are used by the firmware to control allow communication between the firmware (MAC layer) and the device driver. This register set also contains the power down registers. These registers are only accessible through the 80188 core; they are inaccessible from the system interface.
AMD PRELIMINARY SIR0: General Configuration Register (GCR) This register is used to control general functions related to the Am79C930, particularly interrupts to and from the 80188 core and power down functions. Bit Name Reset Value 7 SWRESET 0 Software Reset. When SWRESET is set to a 1, the BIU will be RESET, with the exception of the SWRESET bit and the software reset bit in the PCMCIA Card Configuration Register. The 80188 embedded controller will not be reset. TAI will not be reset.
AMD PRELIMINARY 2 INT2EC 0 Interrupt to Embedded Controller. When INT2EC is set to a 1, an interrupt is sent to the 80188 core. INT2EC will stay set at 1 until the 80188 core clears this bit by writing a 1 to bit 3 of the MIR0 register. Writing a 0 to INT2EC will have no effect on the value of INT2EC. 1 ENECINT 0 Enable Embedded Controller Interrupts.
PRELIMINARY AMD SIR2: Local Memory Address Register [7:0] (LMA) This register is the beginning address on the local bus for system interface I/O transfers that are made to the I/O Data Port. This register automatically increments by Bit Name Reset Value 7:0 LMA[7:0] – “1” following each read or write operation of any section of the I/O Data Port. (MA[16:15] will be given the values of BSS[4:3] – memory bank select bits.
AMD PRELIMINARY SIR5: I/O Data Port B (IODPB) This register is a system interface I/O address alias of I/O Data Port A. Bit Name Reset Value 7:0 IODPB[7:0] – Description Aliased to I/O Data Port A. SIR6: I/O Data Port C (IODPC) This register is a system interface I/O address alias of I/O Data Port A. Bit Name Reset Value 7:0 IODPC[7:0] – Description Aliased to I/O Data Port A. SIR7: I/O Data Port D (IODPD) This register is a system interface I/O address alias of I/O Data Port A.
PRELIMINARY AMD 4 PDC 0 Power Down Command. When PDC is set to 1, the power down cycle of the BIU power down state machine will begin. PDC will automatically clear itself after completion of the power down operation. 3 SYSINT 0 System Interrupt. SYSINT Indicates a 1 after the system issues an interrupt command to the 80188 core by writing to the INT2EC bit of the GCR register (SIR0). SYSINT will become cleared to a 0 when the 80188 core writes a 1 to SYSINT. 2 INT2SYS 0 Interrupt To System.
AMD PRELIMINARY MIR3: Power Down Length Count [15:8] (PDLC) This register is used to determine the length of power down cycles. Before execution of the power down sequence, the 80188 core must load the PDLC counter. Bit 0 Name Reset Value PDLC[15:8] 00h Upon execution of the power down sequence, the PDLC value will be counted down to zero and the power down cycle will end. Description Middle 8 bits of the length of the power down counter.
AMD PRELIMINARY MIR8: Flash Wait States This register gives the Flash Wait states. Bit Name Reset Value 7:4 Reserved – Reserved. Must be written as a 0. Reads of this bit produce undefined data. 3 HOSTALLOW 1 When this bit equals 1, then the host can access memory; if 0, then the host access is blocked completely 2 Reserved – Reserved. Must be written as a 0. Reads of this bit produce undefined data.
AMD 6 5:4 3 PRELIMINARY Reserved – Reserved. Must be written as a 0. Reads of this bit produce undefined data. SRAMWAIT[1:0] 11b These bits must be set equal to or greater than the number of wait states that are generated internally in the 80188 core as defined by the programming of the R1 and R0 bits of the 80188 LMCS register. Wait states programmed into SRAMWAIT will cause wait states to be inserted into 80188 access to SRAM and system accesses to SRAM.
PRELIMINARY AMD PCMCIA CCSR is RESET to a 0. If the STSCHGFN bit of TCR15 has been set to a 0, then the value that is written to this bit will be inverted and driven to the STSTCHG pin of the Am79C930 device. The value that is read from this bit always represents the inverse of the current value of the STSTCHG pin of the Am79C930 device. THIS FUNCTION IS ONLY AVAILABLE IN PCMCIA MODE. The complete control of the function of the STSCHG/BALE pin is described in the Multi-Function Pin section.
AMD PRELIMINARY Transceiver Attachment Interface Registers (TIR Space) The Transceiver Attachment Interface (TAI) Unit contains a total of 64 registers. Thirty-two of the registers are directly accessible from the 80188 embedded core and from the system interface through the BIU. The other 32 registers are indirectly accessed by first writing an INDEX value into the TCR Index Register (TIR24) and then executing a read or write operation to the TCR Data Port (TIR25).
AMD PRELIMINARY TIR mapping with SIR1 bit 2 (EIOW) set to “0” = normal TIR window mode. Note that EIOW = 0 is the only setting TIR Register Number TIR Register Name of EIOW that is allowed while operating in ISA PnP mode.
AMD PRELIMINARY TIR mapping with SIR1 bit 2 (EIOW) set to “1” = Expanded TIR window mode. Note that the setting TIR Register Number EIOW = 1 is only allowed while operating in PCMCIA mode.
PRELIMINARY AMD TIR0: Network Control General control for the transceiver device attached to the transceiver interface pins. Bit 7 Name Reset Value LNK pin Description Link LED. The inverse of the LNK bit value is driven onto the LNK pin when the LNK pin has been enabled for output. The value read from LNK will always represent the inversion of the current value of the LNK pin. The control of the function of the LNK pin is described in the Multi-Function Pin section. 6 ACT pin Activity LED.
AMD PRELIMINARY 1 RXDRQ 0 Receive FIFO DMA Request. This bit represents the current value of the RXDRQ signal to the DRQ0 input of the 80188 embedded core. 0 TXDRQ 1 Transmit FIFO DMA Request. This bit represents the current value of the TXDRQ signal to the DRQ1 input of the 80188 embedded core. TIR2: Serial Device TAI Serial Device register. This register is used to control the serial device interface. Bit Name Reset Value Description 7 Reserved – Reserved. Must be written as a 0.
AMD PRELIMINARY The value read from SDD will always represent the current value of the SDDATA pin. The complete control of the function of the SDDATA pin is described in the Multi-Function Pin section. When the fast serial port (TIR3) is used, then the value written to SDD will be exclusive OR’d (XOR) with the data from the FSD bits of TIR3 before the FSD bits are sent to the SDDATA pin.
AMD PRELIMINARY 5 MOREINT 1 MORE Interrupts. MOREINT will become set whenever there are interrupt bits set in Interrupt Register 3 (TCR11). Note that MOREINT bit does not reflect the state of interrupt status bits from Interrupt Register 2 (TIR5). There is an unmask bit for MOREINT, and there are also individual unmask bits for the interrupts in Interrupt Register 3 (TCR11). 4 TXCNT 0 TX Count reached.
PRELIMINARY AMD (Generated from the internal signal stop_d, which indicates that antenna diversity operation has selected an antenna.) Assertion of ALOKI indicates the cessation of antenna diversity activity so that the incoming network signal can be tracked and decoded by the DPLL.
AMD PRELIMINARY TIR8: Transmit Control This register is the Transmitter Control register. Bit Name Reset Value 7 TXRES 0 Transmit Reset. When this bit is set to 1, the internal Transmit Reset signal is asserted. When this bit is set to 0, the internal Transmit Reset signal is deasserted. The transmit FIFO is NOT reset by TXRES. 6 TXFR 0 Transmit FIFO Reset. When this bit is set to 1, the internal Transmit FIFO Reset signal is asserted.
PRELIMINARY AMD TIR9: Transmit Status Transmit Status register. Indicates the current status of the Transmit portion of the TAI. Writes to these bits have no effect. Bit Name Reset Value 7 TXCRC 0 Transmit CRC. TXCRC becomes set when the CRC is being appended to the end of the transmit frame. TXCRC is reset when the transmission of the last bit of the CRC is completed. 6 TXSDD 0 Transmit Start Delimiter. TXSDD becomes set after the Start of Frame Delimiter has been sent.
AMD PRELIMINARY TIR11: Transmit Sequence Control This register is the Transmit Sequence Control. The bits in this register determine the function of the transmit sequence signals. Bit Name Reset Value 7 RXCD pin Description RXC/IRQ10 pin Data. The value that is written to this bit will be driven out to the RXC pin when the RXCEN bit of TCR15 has been set to a 1 and the RXCFN bit of TCR28 has been set to a 0. The value that is read from RXCD represents the current value of the RXC/IRQ10 pin.
AMD PRELIMINARY TIR12: Byte Count Register LSB This register is the Byte count register LSB. This register contains the lower 8 bits of the 12-bit byte count for receive and transmit messages. This is a working Bit Name Reset Value 7:0 BC[7:0] 00h register; access by software is not needed for normal operation. Description Byte Count. Lower eight bits of current byte count for both transmit and receive operations.
AMD PRELIMINARY TIR15: Byte Count Limit MSB This register is the Byte Count Limit MSB register. Bit Name Reset Value Description 7–4 Reserved – Reserved. Must be written as a 0. Reads of this bit produce undefined data. 3–0 BCLT[11:8] 0h Byte Count Limit. Upper 4 bits of byte count limit for both transmit and receive operations, depending upon which operation is currently occurring.
PRELIMINARY 5 4–1 0 AMD RXFOR 0 Receive FIFO Overrun. This bit is set whenever the RX FIFO experiences an overrun. This bit is cleared by resetting the RX FIFO. RXFC[3:0] 0 Receive FIFO Count. These bits indicate the current count of the number of bytes contained in the RX FIFO. The RX FIFO holds 15 bytes. An RXFC value of “0h” indicates an empty RX FIFO. An RXFC value of “Fh” indicates a full RX FIFO. RXBSY 0 RX Busy.
AMD PRELIMINARY TIR21: CRC32 Correct Byte Count MSB This register is the CRC32 Correct Byte Count MSB register. Bit Name Reset Value Description 7–4 Reserved – Reserved. Must be written as a 0. Reads of this bit produce undefined data. 3–0 C32C[11:8] – CRC32 Correct Count. The value in this register indicates the upper 4 bits of the 12-bit byte position when the CRC32 value was last correct.
PRELIMINARY AMD TIR24: TCR Index Register This register is the TCR Index register. This register is used as an address into indirect TAI register space. The value in the TCR Index Register is used as an address that points at one of 64 registers that are accessed through the TCR Data Port. Bit Name Reset Value Description 7:6 Reserved – Reserved. Must be written as a 0. Reads of this bit produce undefined data. 5:0 TCRI[5:0] 00h TCR Index value.
AMD 2 PRELIMINARY ADDA 0 A/D D/A mode.
PRELIMINARY AMD TIR28: RSSI Lower Limit This register is the RSSI Lower Limit register. The value in this register is compared against converted RSSI input values. When the converted RSSI value is equal to or exceeds the value in this register, then an indication will be sent to the clear channel assessment logic. Bit Name Reset Value 7 RSALT 0 RSSI Equal or Above Limit.
AMD PRELIMINARY TIR31: TEST The TAI TEST register is a reserved location. Bit 7 6–0 Name Reset Value Reserved 0 TC[6:0] 00h Description These bit must be set to 0. Do not write to this register. Test Command. The bits in this register are decoded to generate a test mode for the TAI. TAI Configuration Register Space (TCR) The Transceiver Attachment Interface (TAI) Unit contains a total of 64 registers.
AMD PRELIMINARY SD[1:0] Start of Frame Detect Operation Programmed Register 00 Start of Frame Detect Off None 01 Search for 8 bit Start of Frame Delimiter TCR10 10 Search for 16 bit Start of Frame Delimiter TCR9, TCR10 11 Search for 24 bit Start of Frame Delimiter TCR8, TCR9 TCR10 TCR1: Transmit Configuration This register is the Transmit Configuration register. CONFIGURATION REGISTER INDEX: 01h Bit Description Name Reset Value 7 TXENDCB 0 Transmit Enable DC Bias Control.
AMD PRELIMINARY TCR2: Clock Recovery This register is Configuration register. Bit Name the Clock Reset Value Recovery Description CONFIGURATION REGISTER INDEX: 02h 7 WNS2 0 Bit Stuffing Start. When WNS2 is set to a 1, then the bit stuffing operation on RX and TX frames will begin after the PHY header field has passed. When WNS2 is set to a 0, then the bit stuffing function on RX and TX frames will begin operation immediately following Start of Frame Delimiter detection.
PRELIMINARY AMD to delay the start of CRC8 and CRC32 and DC bias control calculation for both receive and transmit frames. The physical header field is assumed to begin after the Start of Frame Delimiter has been detected. TCR4: Antenna Diversity Timer This register is the Antenna Diversity Timer register used to control antenna dwell time during antenna diversity measurements. CONFIGURATION REGISTER INDEX: 04h Bit Description Name Reset Value 7 ANTEN 0 Antenna Diversity Enable.
AMD PRELIMINARY TCR6: TX Ramp Down Timing This register is the TX Ramp Down Timing register. This register determines the ramp down timing of the TX enable signals. CONFIGURATION REGISTER INDEX: 06h Bit Name Reset Value Description 7:4 TGAP3[3:0] 0h Transmit Timing Gap 3. These bits are used to determine the gap between the deassertion of the T3 signal and the deassertion of the T2 signal. T3 and T2 can be used to control the timing of the TXMOD and TXPE pins.
AMD PRELIMINARY In addition, the USER5/IRQ4 pin may be used to produce interrupts to the 80188 embedded controller. This capability is controlled by the ENXCHBSY bit of TCR28 and the CHBSYCU bit of TIR5 and operates independently of the bits mentioned above. The control of the function of the USER5/IRQ4 pin is described in the Multi-Function Pin section. 4–3 U1INTCNT 00b USER1 Interrupt control bits. The USER1/IRQ12 pin can be used to signal an interrupt to the 80188 embedded controller.
AMD PRELIMINARY has also been set to a 1 and the PCMCIA pin is set to 1. The value that is read from this bit represents the current value of the TXDATA pin of the Am79C930 device. A complete description of the control of the function of the TXDATA pin is described in the Multi-Function Pin section. TCR8: Start Delimiter LSB This register is the Start Delimiter LSB register. CONFIGURATION REGISTER INDEX: 08h Bit Name Reset Value Description 7–0 SDLT[7:0] 00h Start of Frame Delimiter.
PRELIMINARY AMD Delimiter may be used for start of frame recognition by appropriate settings of the SD[1:0] bits in the Network Configuration Register (TCR0). Start of Frame detection is performed on the bits in the order that they appear on the medium, with the SDLT LSB, bit 0, being checked against the first bit to arrive at the Am79C930 (RX case) or the first bit to leave the Am79C930 (Tx case) and continuing in that order. TCR11: Interrupt Register 3 This register is the TAI Interrupt Register 3.
AMD PRELIMINARY TCR13: Pin Configuration A This register is the Pin Configuration A register. This register is used to set the state of various pins as outputs or as high impedance inputs. CONFIGURATION REGISTER INDEX: 0Dh Bit Description Name Reset Value 7 LNKEN 1 Link LED Enable. LNKEN can be used to control the function of the LNK LED output. The control of the function of the LNK pin is described in the Multi-Function Pin section. 6 LFPEEN 1 LFPE Enable.
PRELIMINARY AMD value that is present on the LLOCKE pin, regardless of the setting of the PCMCIA pin. The control of the function of the LLOCKE/SA15 pin is described in the Multi-Function Pin section. 5 4:0 Reserved – Reserved. Must be written as a 0. Reads of these bits produce undefined data. USEREN[4:0] 00h USER[4:0] Enable. These five bits are used to determine the direction of the USER[4:0] pins.
AMD PRELIMINARY In addition to these bits, the USER6/IRQ5 pin may be used to produce interrupts to the 80188 embedded controller. This capability is controlled by the ENXSDF bit of TCR28 and the SDFU bit of TIR5 and operates independently of the bits in the table above. 2 USER5EN 0 USER5 Enable. USER5EN, the USER5FN bit of TCR15, the ISA PnP interrupt level select register, the ISA PnP interrupt type register, and the PCMCIA pin are used to determine the function of the USER5IRQ4 pin.
PRELIMINARY AMD TCR17: Baud Detect Lower Limit This register is the Baud Detect Lower Limit register (TCR17). CONFIGURATION REGISTER INDEX: 11h Bit Name Reset Value Description 7–6 Reserved – Reserved. Must be written as a 0. Reads of this bit produce undefined data. 5–0 BDLLT[5:0] 00h Baud Detect Lower Limit. This register is used to program the lower limit for the Baud detection circuit. The lower limit defines the shortest time between like transitions (i.e.
AMD PRELIMINARY edge baud counter. This information should be used to appropriately program the Baud Detect Upper Limit register. The resolution of the value in this register is the period of the CLKIN signal when the CLKGT20 bit of MIR9 is set to 0 or twice the period of the CLKIN signal when the CLKGT20 bit of MIR9 is set to 1. With CLKIN = 20 MHz and CLKGT20=0, a value of 14h (=20 decimal) represents the nominal like transition separation value for a 1Mbit/s network data rate.
PRELIMINARY CONFIGURATION REGISTER INDEX: 15h Bit Name Reset Value Description 3–0 BDRN[3:0] 0h AMD Baud Detect Ratio. These bits are used to set the ratio of good to bad baud detections which will be used as the minimum ratio to determine that a valid signal is present on the medium. The value in this register is treated as a radix 2 positive real number with two decimal places. The lowest practical value possible is 0.25 (=00.01) and the highest practical value is 3.75 (=11.11).
AMD PRELIMINARY CONFIGURATION REGISTER INDEX: 18h Bit Name Reset Value Description 7:6 Reserved – Reserved. Must be written as a 0. Reads of this bit produce undefined data. 5:0 SS[5:0] 00h RSSI Sample Start. The value in this register is used to determine when to capture a sample of the RSSI input for A/D conversion during antenna diversity operation. The register value is a measure of the time of RSSI sample relative to the end of the current antenna dwell time (i.e.
AMD PRELIMINARY 3–0 A2DT[3:0] 1010b A/D sampling Time[3:0]. The value in the A2DT[3:0] field determines the duration of time required to convert the A/D input. Each bit of resolution is equal to 4 times the CLKIN period when the CLKGT20 bit of MIR9 is set to 0 and is equal to 8 times the CLKIN period when the CLKGT20 bit of MIR9 is set to 1. For a 1Mbs data rate with CLKIN = 20 MHz and CLKGT20 = 0, the resolution is 200 n.
AMD PRELIMINARY TCR26: Reserved This register is the TAI reserved location register. CONFIGURATION REGISTER INDEX: 1Ah Bit Name Reset Value Description 7–0 Reserved – Reserved. Must be written as a 0. Reads of this bit produce undefined data. TCR27: TIP LED Scramble This register is the Network Interface Polarity register. This register is used to set the polarity of some of the transceiver interface output pins.
PRELIMINARY AMD be high assert, such that when the TGAP2 counter expires, the TXMOD pin will be driven to a HIGH logic level. TCR28: Clear Channel Assessment Configuration This register is the Clear Channel Assessment Configuration register. The bits in this register are used to determine which features will be used to determine clear channel assessment. CONFIGURATION REGISTER INDEX: 1Ch Bit Description 7 Name Reset Value RXCFN 0 RXC Function.
AMD PRELIMINARY is set to a 0, the Baud Detect Count for Stop Diversity is not used in the stop diversity decision logic. 1 UBDCS 0 Use Baud Detect of Carrier Sense in CCA decision. When this bit is set to a 1, the Baud Detect Count for Carrier Sense becomes one input to the clear channel assessment logic. When this bit is set to a 0, the Baud Detect Count for Carrier Sense is not used in the clear channel assessment decision. 0 URSSI 0 Use RSSI in CCA and Stop Diversity decisions.
AMD PRELIMINARY then a 16-bit deep serial FIFO is inserted into the TX data path. This FIFO allows for some mismatch to be tolerated in the clock rates between the Am79C930 internal transmit clock and the external TXC clock that is connected to the TXC input. Because of this internal FIFO, the appearance of transmit data from the setting of the TXS bit in TIR8 will be delayed by 8 bit times whenever the TXCIN bit has the value of 1.
AMD PRELIMINARY PCMCIA Configuration Option Register PCMCIA CCR Registers and PCMCIA CIS Space Two bytes of attribute memory space have been used by the Am79C930 device for storage of two card configuration registers. These two registers are found at attribute memory locations 800h and 802h. The Configuration Option Register is located at Attribute memory location 800h and the Card Configuration and Status Register is located at Attribute memory location 802h.
PRELIMINARY AMD When written with a 1, the PWRDWN bit generates an interrupt to the 80188, requesting that the 80188 core place the Am79C930 device into the power down state. The interrupt is signaled in MIR0, bit 5. If written with a 0 while in power down mode, power down mode is exited. When written with a 1, value read will remain 0 until the device actually enters the power down mode. 1 Interrupt – Represents the internal interrupt level.
AMD PRELIMINARY ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature: . . . . . . . . . . . . Commercial (C) Devices –65 to +150°C Ambient Temperature Under Bias: . . . –65 to +125°C Temperature (TA) . . . . . . . . . . . . . . . . . 0°C to + 70°C Supply Voltage to AVSS or DVSS (AVDD, DVDD): . . . . . . . . . . . . . . –0.3 to +6 V Supply Voltages (AVDD, VCC, VDDT, VDDU1, VDDU2, VDDM, VDDP, VDD5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AMD PRELIMINARY DC CHARACTERISTICS (continued) 5.0 V Am79C930 DC Characteristics Parameter Symbol Parameter Description Test Conditions IDDPD2 Power Supply Current IDDPD3 CIN CO CCLK Min Max Units Power Down mode CLKIN = internally cutoff, PMX1 = 32.768 kHz, no host interface accesses occurring VIN ≤ VOL or VIN ≥ VOH 40 mA Power Supply Current Power Down mode CLKIN = internally cutoff, PMX1 = 32.
AMD PRELIMINARY ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature: . . . . . . . . . . . . Commercial (C) Devices –65 to +150°C Ambient Temperature Under Bias: . . . –65 to +125°C Temperature (TA) . . . . . . . . . . . . . . . . . 0°C to + 70°C Supply Voltage to AVSS or DVSS (AVDD, DVDD): . . . . . . . . . . . . . . –0.3 to +6 V Supply Voltages (AVDD, VCC, VDDT, VDDU1, VDDU2, VDDM, VDDP, VDD5) . . . . . . . . . . . . . . . . . . . . . . 3.0 V to 3.
AMD PRELIMINARY DC CHARACTERISTICS (continued) 3.3 V Am79C930 DC Characteristics Parameter Symbol Parameter Description Test Conditions IDDPD2 Power Supply Current IDDPD3 CIN CO CCLK Min Max Units Power Down mode CLKIN = internally cutoff, PMX1 = 32.768 kHz, no host interface accesses occurring VIN ≤ VIL or VIN ≥ VOH 5 mA Power Supply Current Power Down mode CLKIN = internally cutoff, PMX1 = 32.
AMD PRELIMINARY ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature: . . . . . . . . . . . . Commercial (C) Devices –65 to +150°C Ambient Temperature Under Bias: . . . –65 to +125°C Temperature (TA) . . . . . . . . . . . . . . . . . 0°C to + 70°C Supply Voltage to AVSS or DVSS (AVDD, DVDD): . . . . . . . . . . . . . . –0.3 to +6 V Supply Voltages (VCC, VDDT, VDDU1, VDDU2, VDDM, VDDP) . . . . . . . . . . . . . . . . . . . . +5 V ± 5% or 3.0 V to 3.
AMD PRELIMINARY AC CHARACTERISTICS 5.0 AND 3.3 V PCMCIA INTERFACE ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature: . . . . . . . . . . . . Supply Voltages (VCC, VDDT, VDDU1, VDDU2, VDDM, VDDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 V to 5.25 V Commercial (C) Devices Temperature (TA) . . . . . . . . . . . . . . . . . 0°C to + 70°C –65 to +150*C Ambient Temperature Under Bias: . . . –65 to +125*C Supply Voltage to AVSS or DVSS (AVDD, DVDD): . . . . . . . . . . .
AMD PRELIMINARY PCMCIA MEMORY WRITE ACCESS Parameter Symbol Parameter Description Test Conditions Min Max Unit tAVWL Address setup to WE ↓ 20 ns tAVWH Address setup to WE ↑ 100 ns tWMAX Write recovery time (Address hold from WE ↑ ) 20 ns tELWH CE setup to WE ↑ 140 ns 0 ns tELWL CE setup to WE ↓ tGHEH CE hold from OE ↑ (READ) or CE hold from WE ↑ (WRITE) 20 ns tGHWL OE setup to WE ↓ 10 ns tWHGL OE hold from WE ↑ 10 ns tWLWH WE pulse width 120 ns tWLWTV WAIT valid
AMD PRELIMINARY PCMCIA I/O READ ACCESS Parameter Symbol Parameter Description Test Conditions Min Max Unit tAVIGL Address setup to IORD ↓ 70 ns tIGHAX Address hold from IORD ↑ 20 ns tRGLIGL REG setup to IORD ↓ 5 ns tIGHRGH ns REG hold from IORD ↑ 0 tELIGL CE setup to IORD ↓ 5 ns tIGHEH CE hold from IORD ↑ 20 ns tIGLIGH IORD width 165 tIGLIAL INPACK ↓ delay from IORD ↓ tIGHIAH INPACK ↑ delay from IORD ↑ tIGLWTL WAIT ↓ delay from IORD ↓ tWTLWTH WAIT width tWTHQV Dat
AMD PRELIMINARY PCMCIA I/O WRITE ACCESS Parameter Symbol Parameter Description Test Conditions Min Max Unit tAVIWL Address setup to IOWR ↓ 70 ns tIWHAX Address hold from IOWR ↑ 20 ns tRGLIWL REG setup to IOWR ↓ 5 ns tIWHRGH REG hold from IOWR ↑ 0 ns tELIWL CE setup to IOWR ↓ 5 ns tIWHEH CE hold from IOWR ↑ 20 ns 165 tIWLIWH IOWR width tIWLWTL WAIT ↓ delay from IOWR ↓ tWTLWTH WAIT width Notes 1, 2 ns 35 ns 53 X TCLKIN ns tWTHIWH IOWR ↑ from WAIT ↑ 0 ns tDVIWL
PRELIMINARY AC CHARACTERISTICS OPERATING RANGES 5.0 AND 3.3 V ISA INTERFACE ABSOLUTE MAXIMUM RATINGS Commercial (C) Devices Storage Temperature: . . . . . . . . . . . . AMD Temperature (TA) . . . . . . . . . . . . . . . . . 0°C to + 70°C –65 to +150°C Ambient Temperature Under Bias: . . . –65 to +125°C Supply Voltage to AVSS or DVSS (AVDD, DVDD): . . . . . . . . . . . . . . –0.3 to +6 V Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure.
AMD PRELIMINARY ISA ACCESS Parameter Symbol Parameter Description Test Conditions Min Max Unit ti1 LA[23:17] valid setup to BALE ↓ 60 ti2 BALE ↑ to BALE ↓ pulse width 25 ns ti3 LA[23:17] valid hold from BALE ↓ 12 ns ti4 LA[23:17] valid setup to CMD ↓ Note 1 80 ns ti7 SA[16:0] valid setup to CMD ↓ Note 1 25 ns ti8 CMD ↓ to CMD ↑ pulse width Note 4 6*TCLKIN ns ns ti9 SA[16:0] valid setup to BALE ↓ ti10 Data valid delay from RCMD ↓ Notes 2, 5, 6 ti11 Data valid setup to
AMD PRELIMINARY AC CHARACTERISTICS 5.0 V MEMORY BUS INTERFACE ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature: . . . . . . . . . . . . Supply Voltages (VCC, VDDT, VDDU1, VDDU2, VDDM, VDDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75 V to 5.25 V Commercial (C) Devices Temperature (TA) . . . . . . . . . . . . . . . . . 0°C to + 70°C –65 to +150°C Ambient Temperature Under Bias: . . . –65 to +125°C Supply Voltage to AVSS or DVSS (AVDD, DVDD): . . . . . . . . . . . . . .
AMD PRELIMINARY MEMORY BUS WRITE ACCESS Parameter Symbol Parameter Description Test Conditions Max Unit 2 60 ns 2 60 ns 60 ns 60 ns tmAD MA[16:0] valid from CLKIN ↓ tmCD CE active delay from CLKIN ↓ tmWD MWE active delay from CLKIN ↓ 2 tmCQ MD[16:0] driven from CLKIN ↓ 2 tmCV MD[16:0] valid from CLKIN ↓ tmAS Address Setup Time to MWE ↓ tmAW Address Write Access Time (Note 3) tmCW tmWP Note 1 ns TCLKIN-20 ns 0 wait states 1 wait state 2 wait states 95 145 195 ns ns ns
AMD PRELIMINARY AC CHARACTERISTICS 3.3 V MEMORY BUS INTERFACE OPERATING RANGES ABSOLUTE MAXIMUM RATINGS Temperature (TA) . . . . . . . . . . . . . . . . . 0°C to + 70°C Storage Temperature: . . . . . . . . . . . . Supply Voltages (VCC,VDDT, VDDU1, VDDU2, VDDM, VDDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 V to 5.25 V Commercial (C) Devices –65 to +150°C Ambient Temperature Under Bias: . . . –65 to +125°C Supply Voltage to AVSS or DVSS (AVDD, DVDD): . . . . . . . . . . . . .
AMD PRELIMINARY MEMORY BUS WRITE ACCESS Parameter Symbol Parameter Description Test Conditions Max Unit 2 100 ns 2 100 ns 100 ns tmAD MA[16:0] valid from CLKIN ↓ tmCD CE active delay from CLKIN ↓ tmWD MWE active delay from CLKIN ↓ 2 tmCQ MD[7:0] driven from CLKIN ↓ 2 tmCV MD[7:0] valid from CLKIN ↓ tmAS Address Setup Time to MWE ↓ tmAW Address Write Access Time (Note 3) tmCW tmWP Note 1 ns 100 ns TCLKIN-20 ns 0 wait states 1 wait state 2 wait states 160 260 360 ns ns
PRELIMINARY AMD AC CHARACTERISTICS 5.0 V TAI INTERFACE OPERATING RANGES ABSOLUTE MAXIMUM RATINGS Temperature (TA) . . . . . . . . . . . . . . . . . 0°C to + 70°C Storage Temperature: . . . . . . . . . . . . Supply Voltages (VCC,VDDT, VDDU1, VDDU2, VDDM, VDDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 V to 5.25 V Commercial (C) Devices –65 to +150°C Ambient Temperature Under Bias: . . . –65 to +125°C Supply Voltage to AVSS or DVSS (AVDD, DVDD): . . . . . . . . . . . . . . –0.
AMD PRELIMINARY 5.
PRELIMINARY AMD Notes: 1. Only applicable when TXC has been configured as an INPUT. 2. Only applicable when TXC has been configured as an OUTPUT. 3. MIN value not tested. 4. Parameter calculated from other parameters. 5. Clock period must correlate to data rate as specified in DR bits of TCR30. Note that data rate is a function of DR and TCLKIN and CLKGT20 bit of MIR9. 6. The values for these parameters are given for the case with CLKP = 0 (TCR2[4:0]).
AMD PRELIMINARY AC CHARACTERISTICS 3.3 V TAI INTERFACE OPERATING RANGES ABSOLUTE MAXIMUM RATINGS Temperature (TA) . . . . . . . . . . . . . . . . . 0°C to + 70°C Storage Temperature: . . . . . . . . . . . . Supply Voltages (VCC,VDDT, VDDU1, VDDU2, VDDM, VDDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 V to 5.25 V Commercial (C) Devices –65 to +150°C Ambient Temperature Under Bias: . . . –65 to +125°C Supply Voltage to AVSS or DVSS (AVDD, DVDD): . . . . . . . . . . . . . . –0.
AMD PRELIMINARY 3.
AMD PRELIMINARY AC CHARACTERISTICS 5.0 AND 3.3 V USER PROGRAMMABLE PINS ABSOLUTE MAXIMUM RATINGS Storage Temperature: . . . . . . . . . . . . OPERATING RANGES Commercial (C) Devices Temperature (TA) . . . . . . . . . . . . . . . . . 0°C to + 70°C –65 to +150°C Ambient Temperature Under Bias: . . . –65 to +125°C Supply Voltage to AVSS or DVSS (AVDD, DVDD): . . . . . . . . . . . . . . –0.3 to +6 V Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure.
AMD PRELIMINARY AC CHARACTERISTICS 5.0 AND 3.3 V IEEE 1149.1 INTERFACE OPERATING RANGES ABSOLUTE MAXIMUM RATINGS Temperature (TA) . . . . . . . . . . . . . . . . . 0°C to + 70°C Storage Temperature: . . . . . . . . . . . . Supply Voltages (VCC,VDDT, VDDU1, VDDU2, VDDM, VDDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 V to 5.25 V Commercial (C) Devices –65 to +150°C Ambient Temperature Under Bias: . . . –65 to +125°C Supply Voltage to AVSS or DVSS (AVDD, DVDD): . . . . . . . .
AMD PRELIMINARY TIMING WAVEFORMS PCMCIA Bus Interface Waveforms tAVQV tGHAX An, REG tELQV CE tELGL tGHEH tGLQV OE tAVGL WE tGLWTV (high) WAIT tWTLWTH tGHQZ tQVWTH tGLQNZ Do (Dout) 20138B-10 Figure 4. PCMCIA MEMORY READ Access Timing Diagram tAVWH An, REG tWMAX tELWH CE tELWL tGHEH OE tWHGL tWLWH WE tAVWL tWLWTV tWTHWH tWTLWTH WAIT tGHWL tDVWH tWMDX Di (Din) tGHQZ tWLQZ tWHQNZ Do (Dout) tGLQNZ 20138B-11 Figure 5.
AMD PRELIMINARY An tAVIGL tIGHAX REG tRGLIGL tIGHRGH CE tIGHEH tELIGL IORD tIGLIGH tIGLIAL tIGHIAH INPACK tWTHQV tIGLWTL WAIT tWTLWTH tIGHQX tIGLQV tIGQNZ Do (Dout) tIGHQZ 20138B-12 Figure 6. PCMCIA I/O READ Access Timing Diagram An tAVIWL tIWHAX REG tRGLIWL tIWHRGH CE tELIWL IOWR tIWHEH tIWLIWH tIWLWTL WAIT tWTHIWH tWTLWTH tDVIWL tIWHDX Di (Din) 20138B-13 Figure 7.
AMD PRELIMINARY ISA Bus Interface Waveforms ti1 ti3 LAn ti9 SAn ti2 ti12 BALE AEN ti30 ti32 ti26 ti23 ti31 ti10 ti7 ti13 CMD** ti8 ti4 ti20 IOCHRDY ti22 ti21 ti34 ti25 ti16 ti14 SDout (read) ti11 ti15 SDin (write) 20138B-14 **CMD = one of: MEMR, MEMW, IOR, IOW Figure 8.
AMD PRELIMINARY Memory Bus Interface Waveforms CLKIN CLKOUT (internal) tmAH tmAD MAn tmAD tmAA tmACS FCE, SCE, XCE tmRI tmCD tmCD tmOE tmCH MOE tmOD tmOD MWE (high) tmHZ tmRDHC tmH tmRDSC tmOLZ valid MDi (Din) data sampled at this point 20138B-15 Figure 9.
AMD PRELIMINARY CLOCK WAVEFORMS tCLIN 2.0 V tCHIN CLKIN 0.8 V 0.8 V tINLH tINHL tCLKIN tCLTX 2.0 V tCHTX TXC 0.8 V 0.8 V tTXLH tTXHL tTXC tCLRX 2.0 V tCHRX RXC 0.8 V 0.8 V tRXLH tRXHL tRXC Figure 11.
PRELIMINARY AMD TAI WAVEFORMS CLKIN CLKOUT (internal) tn1 ICO* tn2 RCO** tn3 RCO** tn4 RCO** 20138B-18 **ICO = Internally Controlled Output Figure 12. TAI Timing Diagram RXC tRXDS tRXDS RXD TXC (input) tTXDD TXD TXC (output) tTXDV tTXDS tTXDH TXD 20138B-19 Figure 13.
AMD PRELIMINARY PROGRAMMABLE INTERFACE WAVEFORMS CLKIN CLKOUT (internal) WAIT or IOCHRDY tu1 RCO** (data change) RCO** (drive change) tu2 tu3 RCO** (drive change) 20138B-20 **RCO = Register Controlled Output Figure 14.
AMD PRELIMINARY IEEE 1149.1 INTERFACE WAVEFORMS t25 TCK t30 t31 TDI, TMS t32 TDO t34 t35 Output Signals t36 t37 Input Signals 20138B-21 Figure 15. IEEE 1149.
AMD PRELIMINARY AC TEST REFERENCE WAVEFORMS 5.0 V PCMCIA AC Test Reference Waveform This waveform indicates the AC testing method employed for all signals that are PCMCIA bus signals when 2.8 input 0.5 the PCMCIA power supply pins are set to 5.0 V (i.e., VDDP pins = 5.0 V). 2.4 0.8 2.8 2.4 output 0.8 0.5 measured parameter value 20138B-22 Figure 16. 5.0 V PCMCIA AC Test Reference Waveform 3.
AMD PRELIMINARY 5.0 V NON-PCMCIA AC TEST REFERENCE WAVEFORM This waveform indicates the AC testing method employed for all signals that are not PCMCIA bus signals when the appropriate power supply pins are set to 5.0 V (i.e., VDDT, VDDU1, VDDU2, VDDM pins = 5.0 V). 2.4 input 0.45 This includes ISA signals, TAI interface signals, Memory Bus Interface signals, IEEE 1149.1 signals and any other signal not considered to be part of the PCMCIA bus interface. 2.0 0.8 2.4 2.0 output 0.8 0.
AMD PRELIMINARY PHYSICAL DIMENSIONS PQT144 144-Pin Thin Quad Flat Pack (measured in millimeters) 144 1 21.80 22.20 19.80 20.20 19.80 20.20 21.80 22.20 11° – 13° 1.35 1.45 1.60 MAX 1.00 REF. 0.17 0.27 11° – 13° 0.50 BSC 16-038-PQT-2_AH PQT144 5-4-95 ae *For reference only. BSC is an ANSI standard for Basic Space Centering. Trademarks Copyright 1997 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
APPENDIX A Typical Am79C930 System Application 128K Flash Host Computer PCMCIA or ISA PnP Interface 128K SRAM Am79C930 Radio or IR Transceiver 20183A-1 Figure 1: Typical Am79C930 System Application The typical Am79C930 application contains a Am79C930 device, a Flash memory device (up to 128 Kbytes), an SRAM memory device (up to 128 Kbytes), a network transceiver unit, and a host computer system connected to the Am79C930 subsystem through either the PCMCIA or ISA Plug and Play system bus.
AMD 1. Command and status communication 2. Data buffer areas 3. Am79C930 80188 core variable space After performing these functions, the device driver will enable the 80188 core by writing to a register to release the RESET of the Am79C930 80188 core. The Am79C930 80188 core will then begin fetching instructions from the Flash memory and will eventually execute code that causes it to recognize the command area that the driver has set up in the SRAM.
Trademarks Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Am186, Am386, Am486, Am29000, bIMR, eIMR, eIMR+, GigaPHY, HIMIB, ILACC, IMR, IMR+, IMR2, ISA-HUB, MACE, Magic Packet, PCnet, PCnet-FAST, PCnet-FAST+, PCnet-Mobile, QFEX, QFEXr, QuASI, QuEST, QuIET, TAXIchip, TPEX, and TPEX Plus are trademarks of Advanced Micro Devices, Inc. Microsoft is a registered trademark of Microsoft Corporation.