Datasheet

AD9523 Data Sheet
Rev. C | Page 14 of 60
Pin
No. Mnemonic Type
1
Description
12 LDO_PLL2 P/O
LDO Decoupling Pin for PLL2 1.8 V Internal Regulator. Connect a 0.47 F decoupling capacitor from
this pin to ground. Note that for best performance, the LDO bypass capacitor must be placed in close
proximity to the device.
13 VDD3_PLL2 P 3.3 V Supply for PLL2.
14 LDO_VCO P/O
2.5 V LDO Internal Regulator Decoupling Pin for VCO. Connect a 0.47 µF decoupling capacitor from
this pin to ground. Note that, for best performance, the LDO bypass capacitor must be placed in
close proximity to the device.
15
PD
I Chip Power-Down, Active Low. This pin has an internal 40 kΩ pull-up resistor.
16 REF_SEL I Reference Input Select. This pin has an internal 40 kΩ pull-down resistor.
17
SYNC
I
Manual Synchronization. This pin initiates a manual synchronization and has an internal 40 kΩ pull-up
resistor.
18 VDD3_REF P 3.3 V Supply for Output Clock Drivers Reference.
19
RESET
I
Digital Input, Active Low. Resets internal logic to default states. This pin has an internal 40 kΩ pull-up
resistor.
20
CS
I Serial Control Port Chip Select, Active Low. This pin has an internal 40 kΩ pull-up resistor.
21 SCLK/SCL I
Serial Control Port Clock Signal for SPI Mode (SCLK) or I
2
C Mode (SCL). Data clock for serial program-
ming. This pin has an internal 40 kΩ pull-down resistor in SPI mode but is high impedance in I²C mode.
22 SDIO/SDA I/O Serial Control Port Bidirectional Serial Data In/Data Out for SPI Mode (SDIO) or I²C Mode (SDA).
23 SDO O
Serial Data Output. Use this pin to read data in 4-wire mode (high impedance in 3-wire mode). There
is no internal pull-up/pull-down resistor on this pin.
24 REF_TEST I Test Input to PLL1 Phase Detector.
25
OUT13
O
Complementary Square Wave Clocking Output 13. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
26 OUT13 O
Square Wave Clocking Output 13. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
27 VDD3_OUT[12:13] P 3.3 V Supply for Output 12 and Output 13 Clock Drivers.
28
OUT12
O
Complementary Square Wave Clocking Output 12. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
29 OUT12 O
Square Wave Clocking Output 12. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
30 VDD1.8_OUT[12:13] P 1.8 V Supply for Output 12 and Output 13 Clock Dividers.
31
OUT11
O
Complementary Square Wave Clocking Output 11. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
32 OUT11 O
Square Wave Clocking Output 11. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
33 VDD3_OUT[10:11] P 3.3 V Supply for Output 10 and Output 11 Clock Drivers.
34
OUT10
O
Complementary Square Wave Clocking Output 10. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
35 OUT10 O
Square Wave Clocking Output 10. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
36 VDD1.8_OUT[10:11] P 1.8 V Supply for Output 10 and Output 11 Clock Dividers.
37
OUT9
O
Complementary Square Wave Clocking Output 9. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
38 OUT9 O
Square Wave Clocking Output 9. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
39 VDD3_OUT[8:9] P 3.3 V Supply for Output 8 and Output 9 Clock Drivers.
40
OUT8
O
Complementary Square Wave Clocking Output 8. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
41 OUT8 O
Square Wave Clocking Output 8. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
42 VDD1.8_OUT[8:9] P 1.8 V Supply for Output 8 and Output 9 Clock Dividers.
43
OUT7
O
Complementary Square Wave Clocking Output 7. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
44 OUT7 O
Square Wave Clocking Output 7. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
45 VDD3_OUT[6:7] P 3.3 V Supply for Output 6 and Supply Output 7 Clock Drivers.