Datasheet

AD9577 Data Sheet
Rev. 0 | Page 12 of 44
TIMING CHARACTERISTICS
Table 7.
Parameter Min Typ Max Unit Test Conditions/Comments
LVPECL (see Figure 2)
Termination = 200 Ω to 0 V, ac-coupled to 50 Ω
oscilloscope; C
LOAD
= 5 pF
Output Rise Time, t
RP
170 225 300 ps 20% to 80%, measured differentially
Output Fall Time, t
FP
170 230 310 ps 80% to 20%, measured differentially
Skew 20 ps
Between the outputs of the same PLL at the
same frequency. SyncCh01/SyncCh23 set to 1
LVDS (see Figure 3) Termination = 100 Ω differential; C
LOAD
= 5 pF
Output Rise Time, t
RL
180 250 340 ps 20% to 80%, measured differentially
Output Fall Time, t
FL
180 260 330 ps 80% to 20%, measured differentially
Skew 20 ps
Between the outputs of the same PLL at the
same frequency; SyncCh01/SyncCh23 set to 1
CMOS (see Figure 4)
Output Rise Time, t
RC
250 680 950 ps
Termination is high impedance active probe,
total C
LOAD
= 5 pF, R
LOAD
= 20 kΩ, 20% to 80%
Output Fall Time, t
FC
350 700 1000 ps
Termination is high impedance active probe,
total C
LOAD
= 5 pF, R
LOAD
= 20 kΩ, 80% to 20%
Skew 20 ps
Between the outputs of the same PLL at the
same frequency; SyncCh01/SyncCh23 set to 1
Timing Diagrams
DIFFERENTIAL
LVPECL
80%
50%
20%
t
RP
V
OD
t
FP
09284-002
Figure 2. LVPECL Timing, Differential
DIFFERENTIAL
LVDS
80%
50%
20%
t
RL
V
OD
t
FL
09284-003
Figure 3. LVDS Timing, Differential
SINGLE-ENDED
CMOS
80%
20%
t
RC
t
FC
09284-004
Figure 4. CMOS Timing, Single-Ended, 5 pF Load