Datasheet

ManualsBrandsANALOG DEVICES ManualsClock & Timing ICsLFCSP 40 WQ

Data Sheet AD9577

Rev. 0 | Page 27 of 44

DETAILED BLOCK DIAGRAM

XTAL

OSC

REFCLK

XT1

XT2

MARGIN

SSCG

MAX_BW

REFSEL

CMOS

AD9577

DIVIDE

1 OR 2

SCL

SDA

I

2

C

CONTROL

22pF

22pF

VCO

2.15GHz

TO

2.55GHz

PFD/CP

THIRD

ORDER LPF

LDO1

DIVIDE BY

80 TO 131

FEEDBACK

DIVIDER

f

PFD

PLL1

N

A

DIVIDE BY

2TO 6

DIVIDE BY

1TO 32

LVPECL/LVDS

REFOUT

OR 2 × CMOS

V0 D0 FORMAT1

DIVIDE BY

2TO 6

DIVIDE BY

1TO 32

LVPECL/LVDS

OR 2 × CMOS

V1 D1

VCO

DIVIDERS

OUTPUT

DIVIDERS

OUTPUT

BUFFERS

VCO

2.15GHz

TO

2.55GHz

PFD/CP

THIRD

ORDER LPF

LDO2

DIVIDE BY

80 TO 131

FEEDBACK

DIVIDER

PLL2

N

B

DIVIDE BY

2TO 6

DIVIDE BY

1TO 32

LVPECL/LVDS

OR 2 × CMOS

V2 D2 FORMAT2

DIVIDE BY

2TO 6

DIVIDE BY

1TO 32

LVPECL/LVDS

OR 2 × CMOS

V3 D3

SDM

VCO

DIVIDERS

OUTPUT

DIVIDERS

OUTPUT

BUFFERS

3-BIT

0

1

FRAC

FRAC_TRIWAVE

SSCG

MOD

f

PFD

CKDIV

FRAC

FRACSTEP

NUMSTEPS

SSCG

TRIWAVE

GENERATOR

FRAC_TRIWAVE

220nF

LDO

4× GND +

PADDLE

14× VS

09284-036

Figure 32. Detailed Block Diagram