Datasheet

AD9577 Data Sheet
Rev. 0 | Page 38 of 44
I
2
C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION
1 0 0 0 0 0 0 X
SLAVE ADDRESS [6:0]
R/W
CTRL
0 = WR
1 = RD
09284-049
Figure 44. Slave Address Configuration
S SLAVE ADDR, LSB = 0 (WR) A(S) A(S) A(S)DATASUB ADDR A(S) PDATA
09284-050
Figure 45. I
2
C Write Data Transfer
S
S = START BIT P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER
A(M) = LACK OF ACKNOWLEDGE BY MASTER
SSLAVE ADDR, LSB = 0 (WR) SLAVE ADDR, LSB = 1 (RD)A(S) A(S)SUB ADDR A(S) DATA A(M) DATA PA(M)
09284-051
Figure 46. I
2
C Read Data Transfer
START BIT
S
STOP BIT
P
ACKACKWR ACK
D0D7A0A7A5A6
SLADDR[4:0]
SLAVE ADDRESS SUB ADDRESS DATA
SUB ADDR[6:1] DATA[6:1]
SCL
SDA
09284-052
Figure 47. I
2
C Data Transfer Timing
t
BUF
SDA
SS
SCL
t
F
t
LOW
t
R
t
F
t
HD;STA
t
HD;DAT
t
SU;DAT
t
HIGH
t
SU;STA
t
SU;STO
t
HD;STA
t
R
09284-053
PS
Figure 48. I
2
C Port Timing Diagram