Datasheet
Data Sheet AD9577
Rev. 0 | Page 17 of 44
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. THE EXPOSED PADDLE ON THIS PACKAGE IS AN ELECTRICAL CONNECTION
AS WELL AS A THERMAL ENHANCEMENT. FOR THE DEVICE TO FUNCTION
PROPERLY, THE PADDLE MUST BE ATTACHED TO GROUND (GND). IT IS
RECOMMENDED THAT A MINIMUM OF NINE VIAS BE USED TO CONNECT THE
PADDLE TO THE PRINTED CIRCUIT BOARD (PCB) GROUND PLANE.
PIN 1
INDICATOR
1VSCA
2VSI2C
3REFOUT
4VSREFOUT
5VSX
6REFCLK
7XT2
8XT1
9REFSEL
10VSCB
23 OUT3P
24 VSFB
25 VSM
26 SSCG
27 VSFA
28 OUT1N
29 OUT1P
30 VSOB1A
22 OUT3N
21 VSOB3B
11
TST1B
12
TST2B
13
LDO
15
GND
17
OUT2N
16
GND
18
OUT2P
19
VSOB2B
20
MARGIN
14
VSVB
33
OUT0N
34
OUT0P
35
GND
36
GND
37
SCL
38
VSVA
39
TST2A
40
MAX_BW
32
VSOB0A
31
SDA
TOP VIEW
(Not to Scale)
AD9577
09284-005
Figure 5. Pin Configuration
Table 15. Pin Function Descriptions
Pin No. Mnemonic Description
1 VSCA PLL1 Power Supply.
2 VSI2C I
2
C Digital Power Supply.
3 REFOUT
CMOS Reference Output.
4 VSREFOUT
Reference Output Buffer Power Supply.
5 VSX
Crystal Oscillator and Input Reference Power Supply.
6 REFCLK
Reference Clock Input. Tie low when not in use.
7, 8 XT2, XT1
External 19.44 MHz to 27 MHz Crystal. Leave unconnected when not in use.
9 REFSEL
Logic Input. Use this pin to select the reference source. Internal 30 kΩ pull-up resistor.
10 VSCB
PLL2 Analog Power Supply.
11 TST1B
Test Pin. Connect this pin to Pin 13 (LDO).
12 TST2B
Test Pin. Connect this pin to Pin 13 (LDO).
13 LDO
This pin is for bypassing the PLL2 LDO to ground with a 220 nF capacitor.
14 VSVB
PLL2 VCO Power Supply.
15, 16, 35, 36 GND
Ground.
17 OUT2N
LVPECL/LVDS/CMOS Clock Output.
18 OUT2P
LVPECL/LVDS/CMOS Clock Output.
19 VSOB2B
Output Port OUT2 Power Supply.
20 MARGIN
Logic 1 sets the margining frequency on the clock output pins. Internal 30 kΩ pull-down resistor.
21 VSOB3B
Output Port OUT3 Power Supply.
22 OUT3N
LVPECL/LVDS/CMOS Clock Output.
23 OUT3P
LVPECL/LVDS/CMOS Clock Output.
24 VSFB
PLL2 Analog Power Supply.
25 VSM
PLL2 Digital Power Supply.
26 SSCG
Logic 1 enables spread spectrum operation of PLL2. Internal 30 kΩ pull-down resistor.
27 VSFA
PLL1 Analog Power Supply.
28 OUT1N
LVPECL/LVDS/CMOS Clock Output.
29 OUT1P LVPECL/LVDS/CMOS Clock Output.