Datasheet

AD9577 Data Sheet
Rev. 0 | Page 18 of 44
Pin No. Mnemonic Description
30 VSOB1A Output Port OUT1 Power Supply.
31 SDA Serial Data Line for I
2
C.
32 VSOB0A Output Port OUT0 Power Supply.
33 OUT0N LVPECL/LVDS/CMOS Clock Output.
34 OUT0P LVPECL/LVDS/CMOS Clock Output.
37 SCL Serial Clock for I
2
C.
38 VSVA PLL1 VCO Power Supply.
39 TST2A Test Pin. Connect this pin to the printed circuit board (PCB) ground plane.
40 MAX_BW
Logic 1 widens the loop bandwidth of the fractional-N PLL during spread spectrum. Internal 30 kΩ pull-
down resistor.
EPAD
The exposed paddle on this package is an electrical connection as well as a thermal enhancement. For
the device to function properly, the paddle must be attached to ground (GND). It is recommended that
a minimum of nine vias be used to connect the paddle to the printed circuit board (PCB) ground plane.