Datasheet
Data Sheet AD9577
Rev. 0 | Page 39 of 44
Table 30. Internal Register Map
Register
Name R/W Addr D7 D6 D5 D4 D3 D2 D1 D0
C0 W 0x40 0 0 0 0 0 0 EnI2C 0
X0 W 0x1F 0 0 0 0 0 0 0 NewAcq
BP0 W 0x11 0 0 0 0 0 Bleed PDCH1 PDCH0
AF0 W 0x18 0 0 Na[5:0], PLL1 feedback divider ratio
BF3 W 0x1C 0 0 Nb[5:0], PLL2 feedback divider ratio
BF0 W 0x19 FRAC[11:4], SDM fractional word
BF1 W 0x1A FRAC[3:0], SDM fractional word MOD[11:8], SDM modulus
BF2 W 0x1B MOD[7:0], SDM modulus
ABF0 W 0x1D 1 1 0 PD_SDM 0 0 0 0
ADV0 W 0x22 V0[2:0], Channel 0 VCO divider D0[4:0], Channel 0 output divider value
ADV1 W 0x23 V1[2:0], Channel 1 VCO divider D1[4:0], Channel 1 output divider value
ADV2 W 0x24 0 0 0 0 0 0 0 SyncCh01
BDV0 W 0x25 V2[2:0], Channel 2 VCO divider D2[4:0], Channel 2 output divider value
BDV1 W 0x26 V3[2:0], Channel 3 VCO divider D3[4:0], Channel 3 output divider value
BDV2 W 0x27 0 0 0 0 0 0 0 SyncCh23
BS1 W 0x2A FracStep[7:0], SSCG fractional step size
BS2 W 0x2B NumSteps[8:1], number of fractional word increments/decrements per half triangular-wave cycle
BS3 W 0x2C NumSteps[0] CkDiv[6:0], reference divider output is divided by this integer to determine SSCG update rate
AM0 W 0x30 0 0 Na[5:0], PLL1 feedback divider ratio divider; MARGIN = 1
AM1 W 0x31 V0[2:0], Channel 0 VCO divider;
MARGIN = 1
D0[4:0], Channel 0 output divider value; MARGIN = 1
AM2 W 0x32 V1[2:0], Channel 1 VCO divider;
MARGIN = 1
D1[4:0], Channel 1 output divider value; MARGIN = 1
BM0 W 0x33 0 0 Nb[5:0], PLL2 feedback divider ratio divider; MARGIN = 1
BM1 W 0x34 FRAC[11:4], SDM fractional word; MARGIN = 1
BM2 W 0x35 FRAC[3:0], SDM fractional word; MARGIN = 1 MOD[11:8], SDM modulus; MARGIN = 1
BM3 W 0x36 MOD[7:0], SDM modulus; MARGIN = 1
BM4 W 0x37 V3[2:0], Channel 3 VCO divider;
MARGIN = 1
D3[4:0], Channel 3 output divider value; MARGIN = 1
BM5 W 0x38 V2[2:0], Channel 2 VCO divider;
MARGIN = 1
D2[4:0], Channel 2 output divider value; MARGIN = 1
DR1 W 0x3A PDCH3 PDCH2 FORMAT2[2:0], output format selection
for PLL2 (see
Table 21)
FORMAT1[2:0], output format selection for
PLL1 (see Table 20)
DR2 W 0x3B 0 0 0 0 0 0 0 PDRefOut
G0 W 0x3D 0 0 0 0 PDPLL1, power-
down PLL1
PDPLL2, power-
down PLL2
R; 0 =
divide by 1
0