SHARC Processor ADSP-21469 SUMMARY The ADSP-21469 processor is available with unique audiocentric peripherals such as the digital applications interface, DTCP (digital transmission content protection protocol), serial ports, precision clock generators, S/PDIF transceiver, asynchronous sample rate converters, input data port, and more.
ADSP-21469 TABLE OF CONTENTS Summary ............................................................... 1 Absolute Maximum Ratings ................................... 20 Revision History ...................................................... 2 ESD Sensitivity ................................................... 20 General Description ................................................. 3 Package Information ............................................ 20 Family Core Architecture .............................
ADSP-21469 GENERAL DESCRIPTION The ADSP-21469 SHARC® processor is a member of the SIMD SHARC family of DSPs that feature Analog Devices’ Super Harvard Architecture. The processor is source code compatible with the ADSP-2126x, ADSP-2136x, ADSP-2137x, and ADSP-2116x DSPs, as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode.
ADSP-21469 • Digital applications interface that includes four precision clock generators (PCG), an input data port (IDP) for serial and parallel interconnect, an S/PDIF receiver/transmitter, four asynchronous sample rate converters, eight serial ports, a flexible signal routing unit (DAI SRU). Timer • Digital peripheral interface that includes two timers, a 2wire interface, one UART, two serial peripheral interfaces (SPI), 2 precision clock generators (PCG) and a flexible signal routing unit (DPI SRU).
ADSP-21469 S JTAG FLAG TIMER INTERRUPT CACHE SIMD Core PM ADDRESS 24 DMD/PMD 64 5 STAGE PROGRAM SEQUENCER PM DATA 48 DAG1 16x32 DAG2 16x32 PM ADDRESS 32 SYSTEM I/F DM ADDRESS 32 USTAT 4x32-BIT PM DATA 64 PX 64-BIT DM DATA 64 MULTIPLIER MRF 80-BIT SHIFTER ALU MRB 80-BIT RF Rx/Fx PEx 16x40-BIT DATA SWAP RF Sx/SFx PEy 16x40-BIT ASTATx ASTATy STYKx STYKy ALU SHIFTER MULTIPLIER MSB 80-BIT MSF 80-BIT Figure 2.
ADSP-21469 floating-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floating-point formats is performed in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers.
ADSP-21469 FAMILY PERIPHERAL ARCHITECTURE VISA and ISA Access to External Memory The ADSP-21469 family contains a rich set of peripherals that support a wide variety of applications including high quality audio, medical imaging, communications, military, test equipment, 3D graphics, speech recognition, motor control, imaging, and other applications. The DDR2 controller on the ADSP-21469 processor supports VISA code operation which reduces the memory load since the VISA instructions are compressed.
ADSP-21469 of memory devices including SRAM, Flash, and EPROM, as well as I/O devices that interface with standard memory control lines. Bank 0 occupies a 2M word window and banks 1, 2, and 3 occupy a 4M word window in the processor’s address space but, if not fully populated, these windows are not made contiguous by the memory controller logic. External Port Throughput The throughput for the external port, based on a 400 MHz clock, is 66M bytes/s for the AMI and 800M bytes/s for DDR2.
ADSP-21469 • DMA (direct memory access) – The DMA controller transfers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. Input Data Port The IDP provides up to eight serial input channels—each with its own clock, frame sync, and data inputs. The eight channels are automatically multiplexed into a single 32-bit by eight-deep FIFO. Data is always formatted as a 64-bit frame and divided into two 32-bit words.
ADSP-21469 Delay Line DMA Table 8. Boot Mode Selection The ADSP-21469 processor provides delay line DMA functionality. This allows processor reads and writes to external delay line buffers (and hence to external memory) with limited core interaction. BOOTCFG2–0 Booting Mode 000 SPI Slave Boot 001 SPI Master Boot Scatter/Gather DMA 010 AMI Boot (for 8-bit Flash boot) The ADSP-21469 processor provides scatter/gather DMA functionality.
ADSP-21469 Target Board JTAG Emulator Connector Evaluation Kit Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-21469 processors to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks.
ADSP-21469 PIN FUNCTION DESCRIPTIONS UNUSED DDR2 PINS When the DDR2 controller is not used: • Power down the receive path by setting the PWD bits of the DDR2PADCTLx register. • Leave the DDR2 signal pins floating. • Connect the VDD_DDR2 pins to the VDD_INT supply. • Internally, three-state the DDR2 I/O signals. This can be done by setting the DIS_DDRCTL bit of DDR2CTL0 register. • Leave VREF floating/unconnected. Table 9.
ADSP-21469 Table 9. Pin Descriptions (Continued) State During/ After Reset Name Type Description DDR2_ADDR15–0 O/T High-Z/driven low DDR2 Address. DDR2 address pins. DDR2_BA2-0 O/T High-Z/driven low DDR2 Bank Address Input. Defines which internal bank an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied to. BA2–0define which mode registers, including MR, EMR, EMR(2), and EMR(3) are loaded during the LOAD MODE REGISTER command.
ADSP-21469 Table 9. Pin Descriptions (Continued) Name Type State During/ After Reset DAI _P20–1 I/O/T (ipu) High-Z Digital Applications Interface. These pins provide the physical interface to the DAI SRU. The DAI SRU configuration registers define the combination of on-chip audiocentric peripheral inputs or outputs connected to the pin and to the pin’s output enable. The configuration registers of these peripherals then determine the exact behavior of the pin.
ADSP-21469 Table 9. Pin Descriptions (Continued) Name Type TDI I (ipu) State During/ After Reset Description Test Data Input (JTAG). Provides serial data for the boundary scan logic. High-Z Test Data Output (JTAG). Serial scan output of the boundary scan path. TDO O /T TMS I (ipu) Test Mode Select (JTAG). Used to control the test state machine. TCK I Test Clock (JTAG). Provides a clock for JTAG boundary scan.
ADSP-21469 Table 10. Pin List, Power and Ground Name Type Description VDD_INT P Internal Power VDD_EXT P External Power VDD_A P Analog Power for PLL VDD_THD P Thermal Diode Power P DDR2 Interface Power VREF P DDR2 Input Voltage Reference GND G Ground AGND G Analog Ground VDD_DDR2 1 1 Applies to DDR2 signals. Rev.
ADSP-21469 SPECIFICATIONS OPERATING CONDITIONS 450 MHz Parameter 1 VDD_INT VDD_EXT VDD_A2 VDD_DDR23, 4 VDD_THD VREF VIH5 VIL5 VIH_CLKIN6 VIL_CLKIN6 VIL_DDR2 (DC) VIH_DDR2 (DC) VIL_DDR2 (AC) VIH_DDR2 (AC) TJ TJ 400 MHz Description Min Nom Max Min Nom Max Unit Internal (Core) Supply Voltage External (I/O) Supply Voltage Analog Power Supply Voltage DDR2 Controller Supply Voltage Thermal Diode Supply Voltage DDR2 Reference Voltage High Level Input Voltage @ VDD_EXT = Max Low Level Input Voltage @ VD
ADSP-21469 ELECTRICAL CHARACTERISTICS 450 MHz Parameter1 2 VOH VOL2 VOH_DDR2 VOL_DDR2 IIH4, 5 IIL4, 6 IILPU5 IIHPD6 IOZH7, 8 IOZL7, 9 IOZLPU8 IOZHPD9 IDD-INTYP10, 11 IDD_A12 CIN13, 14 Description Test Conditions Min 3 High Level Output Voltage Low Level Output Voltage High Level Output Voltage for DDR2 Low Level Output Voltage for DDR2 High Level Input Current Low Level Input Current @ VDD_EXT = Min, IOH = –1.
ADSP-21469 Total Power Dissipation The ASF is combined with the CCLK frequency and VDD_INT dependent data in Table 13 to calculate this part. The second part is due to transistor switching in the peripheral clock (PCLK) domain, which is included in the IDD_INT specification equation. Total power dissipation has two components: 1. Internal power consumption 2. External power consumption Internal power consumption also comprises two components: 1. Static, due to leakage current.
ADSP-21469 Table 13. Baseline Dynamic Current in CCLK Domain (mA, with ASF = 1.0)1 1 2 Voltage (VDD_INT)2 fCCLK (MHz)2 0.95 V 1.0 V 1.05 V 1.10 V 1.15 V 100 78 82 86 91 98 150 115 121 130 136 142 200 150 159 169 177 188 250 186 197 208 219 231 300 222 236 249 261 276 350 259 275 288 304 319 400 293 309 328 344 361 450 N/A N/A 366 385 406 The values are not guaranteed as standalone maximum specifications.
ADSP-21469 TIMING SPECIFICATIONS Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, it is not meaningful to add parameters to derive longer times. See Figure 45 on Page 58 under Test Conditions for voltage reference levels.
PLL CLKIN DIVIDER f INPUT LOOP FILTER VCO PLL DIVIDER XTAL PMCTL (PLLD) BUF PMCTL (INDIV) PLL MULTIPLIER PMCTL (PLLBP) LINK PORT CLOCK DIVIDER LCLK PMCTL (DDR2CKR) CLK_CFGx/ PMCTL fCCLK DDR2 DIVIDER PMCTL (PLLBP) BYPASS MUX PLLI CLK BYPASS MUX CLKIN PMCTL (LCLKR) BYPASS MUX ADSP-21469 CCLK CLK_CFGx/PMCTL (2xPLLM) DIVIDE BY 2 DDR2_CLK PCLK PCLK RESET DELAY OF 4096 CLKIN CYCLES PIN MUX CLKOUT (TEST ONLY) RESETOUT CCLK BUF RESETOUT CORERST Figure 5.
ADSP-21469 Power-Up Sequencing The timing requirements for processor startup are given in Table 17. While no specific power-up sequencing is required between VDD_EXT, VDD_DDR2, and VDD_INT, there are some considerations that the system designs should take into account. sharing these signals on the board must determine if there are any issues that need to be addressed based on this behavior.
ADSP-21469 Clock Input Table 18. Clock Input Parameter Timing Requirements tCK CLKIN Period tCKL CLKIN Width Low tCKH CLKIN Width High tCKRF CLKIN Rise/Fall (0.4 V to 2.0 V) tCCLK5 CCLK Period VCO Frequency fVCO6 tCKJ7, 8 CLKIN Jitter Tolerance 400 MHz1 Max Min 153 7.5 7.5 Min 100 45 45 34 10 900 +250 2.5 200 –250 450 MHz2 Max Unit 100 45 45 34 10 900 +250 ns ns ns ns ns MHz ps 13.26 6.63 6.63 2.22 200 –250 1 Applies to all 400 MHz models. See Ordering Guide on Page 70.
ADSP-21469 Reset Table 19. Reset Parameter Timing Requirements tWRST1 RESET Pulse Width Low tSRST RESET Setup Before CLKIN Low 1 Min Max 4 × tCK 8 Unit ns ns Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 ms while RESET is low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator). CLKIN tWRST tSRST RESET Figure 9.
ADSP-21469 Interrupts The following timing specification applies to the FLAG0, FLAG1, and FLAG2 pins when they are configured as IRQ0, IRQ1, and IRQ2 interrupts as well as the DAI_P20–1 and DPI_P14–1 pins when they are configured as interrupts. Table 21. Interrupts Parameter Timing Requirement tIPW IRQx Pulse Width Min Max 2 × tPCLK + 2 Unit ns INTERRUPT INPUTS tIPW Figure 11. Interrupts Core Timer The following timing specification applies to FLAG3 when it is configured as the core timer (TMREXP).
ADSP-21469 Timer PWM_OUT Cycle Timing The following timing specification applies to Timer0 and Timer1 in PWM_OUT (pulse-width modulation) mode. Timer signals are routed to the DPI_P14–1 pins through the DPI SRU. Therefore, the timing specifications provided below are valid at the DPI_P14–1 pins. Table 23. Timer PWM_OUT Timing Parameter Switching Characteristic tPWMO Timer Pulse Width Output Min Max Unit 2 × tPCLK – 1.2 2 × (231 – 1) × tPCLK ns tPWMO PWM OUTPUTS Figure 13.
ADSP-21469 Pin to Pin Direct Routing (DAI and DPI) For direct pin connections only (for example DAI_PB01_I to DAI_PB02_O). Table 25. DAI and DPI Pin to Pin Routing Parameter Timing Requirement tDPIO Delay DAI/DPI Pin Input Valid to DAI/DPI Output Valid Min Max Unit 1.5 12 ns DAI_Pn DPI_Pn tDPIO DAI_Pm DPI_Pm Figure 15. DAI and DPI Pin to Pin Direct Routing Rev.
ADSP-21469 Precision Clock Generator (Direct Pin Routing) This timing is only valid when the SRU is configured such that the precision clock generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its outputs directly to the DAI pins. For the other cases, where the PCG’s inputs and outputs are not directly routed to/from DAI pins (via pin buffers) there is no timing data available.
ADSP-21469 Flags The timing specifications provided below apply to AMI_ADDR23–0 and AMI_DATA7–0 when configured as FLAGS. See Table 9 on Page 12 for more information on flag use. Table 27. Flags Parameter Timing Requirement tFIPW DPI_P14–1, AMI_ADDR23–0, AMI_DATA7–0, FLAG3–0 IN Pulse Width Switching Characteristic DPI_P14–1, AMI_ADDR23–0, AMI_DATA7–0, FLAG3–0 OUT Pulse Width tFOPW FLAG INPUTS tFIPW FLAG OUTPUTS tFOPW Figure 17. Flags Rev.
ADSP-21469 DDR2 SDRAM Read Cycle Timing Table 28. DDR2 SDRAM Read Cycle Timing, VDD-DDR2 Nominal 1.
ADSP-21469 DDR2 SDRAM Write Cycle Timing Table 29. DDR2 SDRAM Write Cycle Timing, VDD-DDR2 Nominal 1.
ADSP-21469 AMI Read Use these specifications for asynchronous interfacing to memories. Note that timing for AMI_ACK, AMI_DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asynchronous access mode. Table 30. Memory Read Parameter Min Timing Requirements tDAD Address, Selects Delay to Data Valid1, 2 tDRLD AMI_RD Low to Data Valid1 tSDS Data Setup to AMI_RD High 2.
ADSP-21469 AMI_ADDR AMI_MSx tDARL tRW tDRHA AMI_RD tDRLD tSDS tDAD tHDRH AMI_DATA tRWR tDSAK tDAAK AMI_ACK AMI_WR Figure 20. AMI Read Rev.
ADSP-21469 AMI Write Use these specifications for asynchronous interfacing to memories. Note that timing for AMI_ACK, AMI_DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asynchronous access mode. Table 31. Memory Write Parameter Min Max Unit Timing Requirements tDAAK AMI_ACK Delay from Address, Selects1, 2 tDDR2_CLK – 9.7 + W ns 1, 3 tDSAK AMI_ACK Delay from AMI_WR Low W–6 ns Switching Characteristics tDAWH Address, Selects to AMI_WR Deasserted2 tDDR2_CLK – 3.
ADSP-21469 Link Ports Calculation of link receiver data setup and hold relative to link clock is required to determine the maximum allowable skew that can be introduced in the transmission path length difference between LDATA and LCLK. Setup skew is the maximum delay that can be introduced in LDATA relative to LCLK: (setup skew = tLCLKTWH min – tDLDCH – tSLDCL). Hold skew is the maximum delay that can be introduced in LCLK relative to LDATA: (hold skew = tLCLKTWL min – tHLDCH – tHLDCL). Table 32.
ADSP-21469 Table 33. Link Ports—Transmit Parameter Timing Requirements tSLACH LACK Setup Before LCLK Low LACK Hold After LCLK Low tHLACH Switching Characteristics tDLDCH Data Delay After LCLK High tHLDCH Data Hold After LCLK High tLCLKTWL LCLK Width Low tLCLKTWH LCLK Width High tDLACLK LCLK Low Delay After LACK High 1 Min Max 8.5 0 ns ns 1 –1 0.5 × tLCLK – 0.4 0.4 × tLCLK – 0.41 tLCLK – 2 0.6 × tLCLK + 0.41 0.5 × tLCLK + 0.4 tLCLK + 8 For 1:2.5 ratio. For other ratios this specification is 0.
ADSP-21469 Serial Ports In slave transmitter mode and master receiver mode the maximum serial port frequency is fPCLK/8. To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) serial clock (SCLK) width. Serial port signals are routed to the DAI_P20–1 pins using the SRU.
ADSP-21469 DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE DATA RECEIVE—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE tSCLKIW SAMPLE EDGE tSCLKW DAI_P20–1 (SCLK) DAI_P20–1 (SCLK) tDFSIR tDFSE tSFSI tHOFSIR tHFSI DAI_P20–1 (FS) tSFSE tHFSE tSDRE tHDRE tHOFSE DAI_P20–1 (FS) tSDRI tHDRI DAI_P20–1 (DATA CHANNEL A/B) DAI_P20–1 (DATA CHANNEL A/B) DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE DATA TRANSMIT—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE tSCLKIW SAMPLE EDGE tSCLKW DAI_P20–1 (SCLK) DAI_P20–1 (SCLK) t
ADSP-21469 Table 36. Serial Ports—Enable and Three-State Parameter Switching Characteristics tDDTEN1 Data Enable from External Transmit SCLK Data Disable from External Transmit SCLK tDDTTE1 tDDTIN1 Data Enable from Internal Transmit SCLK 1 Min Unit 11.5 ns ns ns 2 –1 Referenced to drive edge. DRIVE EDGE DRIVE EDGE DAI_P20–1 (SCLK, EXT) tDDTEN tDDTTE DAI_P20–1 (FRAME SYNC) DRIVE EDGE DAI_P20–1 (DATA CHANNEL A/B) tDDTIN Figure 25. Serial Ports—Enable and Three-State Rev.
ADSP-21469 The SPORTx_TDV_O output signal (routing unit) becomes active in SPORT multichannel mode. During transmit slots (enabled with active channel selection registers) the SPORTx_TDV_O is asserted for communication with external devices. Table 37.
ADSP-21469 Table 38. Serial Ports—External Late Frame Sync Parameter Switching Characteristics tDDTLFSE1 Data Delay from Late External Transmit Frame Sync or External Receive Frame Sync with MCE = 1, MFD = 0 tDDTENFS1 Data Enable for MCE = 1, MFD = 0 1 Min Max 7.75 ns ns 0.5 The tDDTLFSE and tDDTENFS parameters apply to left-justified as well as DSP serial mode, and MCE = 1, MFD = 0.
ADSP-21469 Input Data Port (IDP) The timing requirements for the IDP are given in Table 39. IDP signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 39.
ADSP-21469 PDAP chapter of the ADSP-214xx SHARC Processor Hardware Reference. Note that the 20 bits of external PDAP data can be provided through the AMI_ADDR23–4 pins or over the DAI pins. Parallel Data Acquisition Port (PDAP) The timing requirements for the PDAP are provided in Table 40. PDAP is the parallel mode operation of channel 0 of the IDP. For details on the operation of the PDAP, see the Table 40.
ADSP-21469 Sample Rate Converter—Serial Input Port The ASRC input signals are routed from the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided in Table 41 are valid at the DAI_P20–1 pins. Table 41.
ADSP-21469 Sample Rate Converter—Serial Output Port For the serial output port, the frame sync is an input and it should meet setup and hold times with regard to the serial clock on the output port. The serial data output has a hold time and delay specification with regard to serial clock. Note that the serial clock rising edge is the sampling edge, and the falling edge is the drive edge. Table 42.
ADSP-21469 Pulse-Width Modulation (PWM) Generators The following timing specifications apply when the AMI_ADDR23–8 pins are configured as PWM. Table 43. Pulse-Width Modulation (PWM) Timing Parameter Switching Characteristics tPWMW PWM Output Pulse Width tPWMP PWM Output Period Min Max Unit tPCLK – 2 2 × tPCLK – 1.5 (216 – 2) × tPCLK – 2 (216 – 1) × tPCLK – 1.5 ns ns tPWMW PWM OUTPUTS tPWMP Figure 32. PWM Timing Rev.
ADSP-21469 S/PDIF Transmitter Serial data input to the S/PDIF transmitter can be formatted as left-justified, I2S, or right-justified with word widths of 16, 18, 20, or 24 bits. The following sections provide timing for the transmitter. S/PDIF Transmitter-Serial Input Waveforms Figure 34 shows the default I2S-justified mode. LRCLK is low for the left channel and HI for the right channel. Data is valid on the rising edge of serial clock. The MSB is left-justified to an LRCLK transition but with a delay.
ADSP-21469 Table 46. S/PDIF Transmitter Left-Justified Mode Parameter Timing Requirement tLJD LRCLK to MSB Delay in Left-Justified Mode DAI_P20–1 LRCLK LEFT/RIGHT CHANNEL DAI_P20–1 SCLK tLJD DAI_P20–1 SDATA MSB MSB–1 MSB–2 LSB+2 LSB+1 Figure 35. Left-Justified Mode Rev.
ADSP-21469 S/PDIF Transmitter Input Data Timing The timing requirements for the S/PDIF transmitter are given in Table 47. Input signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 47.
ADSP-21469 S/PDIF Receiver The following section describes timing as it relates to the S/PDIF receiver. Internal Digital PLL Mode In the internal digital phase-locked loop mode the internal PLL (digital PLL) generates the 512 × FS clock. Table 49.
ADSP-21469 SPI Interface—Master The ADSP-21469 contains two SPI ports. Both primary and secondary are available through DPI only. The timing provided in Table 50 and Table 51 applies to both. Table 50.
ADSP-21469 SPI Interface—Slave Table 51.
ADSP-21469 Media Local Bus All the numbers given are applicable for all speed modes (1024 Fs, 512 Fs, and 256 Fs for 3-pin; 512 Fs and 256 Fs for 5pin) unless otherwise specified. Please refer to MediaLB specification document rev 3.0 for more details. Table 52.
ADSP-21469 MLBSIG/ MLBDAT (Rx, Input) VALID tDHMCF tDSMCF tMLBCLK tMCKH tMCKL MLBCLK tMCKF tMCKR tMCDRV tMCFDZ MLBSIG/ MLBDAT (Tx, Output) tMDZH VALID Figure 40. MLB Timing (3-Pin Interface) Table 53.
ADSP-21469 MLBSIG, MLBDAT (Rx, Input) VALID tDSMCF tDHMCF tMLBCLK tMCKH tMCKL MLBCLK tMCKF tMCKR tMCDRV tMCRDL MLBSO, MLBDO (Tx, Output) VALID Figure 41. MLB Timing (5-Pin Interface) MLBCLK tMPWV Figure 42. MLB 3-Pin and 5-Pin MLBCLK Pulse Width Variation Timing Rev.
ADSP-21469 Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing For information on the UART port receive and transmit operations, see the ADSP-214xx SHARC Hardware Reference Manual. 2-Wire Interface (TWI)—Receive and Transmit Timing For information on the TWI receive and transmit operations, see the ADSP-214xx SHARC Hardware Reference Manual. JTAG Test Access Port and Emulation Table 54.
ADSP-21469 TEST CONDITIONS OUTPUT DRIVE CURRENTS The ac signal specifications (timing parameters) appear in Table 19 on Page 25 through Table 54 on Page 57. These include output disable time, output enable time, and capacitive loading. The timing specifications for the SHARC apply for the voltage reference levels in Figure 44. Figure 46 and Figure 46 shows typical I-V characteristics for the output drivers of the ADSP-21469, and Table 55 shows the pins associated with each driver.
ADSP-21469 50 14 TYPE C & D, FULL DRIVE 12 VOH 3.13 V, 125 °C 30 20 RISE AND FALL TIMES (ns) SOURCE (VDDEXT) CURRENT (mA) 40 TYPE C & D, HALF DRIVE 10 0 TYPE C & D, HALF DRIVE -10 -20 -30 VOL 3.13 V, 125 °C TYPE C & D, FULL DRIVE 0.5 0 1.0 10 TYPE A RISE y = 0.0572x + 0.5571 8 TYPE B FALL y = 0.0278x + 0.3138 6 4 TYPE B RISE y = 0.0258x + 0.3684 2 -40 -50 TYPE A FALL y = 0.0746x + 0.5146 0 1.
4 4.5 3.5 4 TYPE C & D HALF DRIVE FALL y = 0.0841x + 0.8997 3 TYPE C & D HALF DRIVE RISE y = 0.0617x + 0.7995 2.5 TYPE C & D FULL DRIVE FALL y = 0.0421x + 0.9257 2 1.5 TYPE C & D FULL DRIVE RISE y = 0.0304x + 0.8204 1 RISE AND FALL DELAY (ns) RISE AND FALL TIMES (ns) ADSP-21469 TYPE A RISE y = 0.0152x + 1.7611 3.5 TYPE B RISE y = 0.0060x + 1.7614 3 2.5 TYPE B FALL 2 y = 0.0074x + 1.421 1.5 1 0.5 0 TYPE A FALL y = 0.0196x + 1.2934 0.
ADSP-21469 1.4 3.0 TYPE D HALF DRIVE TRUE (FALL) TYPE D HALF DRIVE COMP (FALL) y = 0.0123x + 2.3194 1.3 2.6 2.4 2.2 2.0 TYPE D HALF DRIVE COMP (RISE) y = 0.0077x + 2.2398 TYPE D FULL DRIVE COMP (RISE) y = 0.0022x + 2.1499 1.8 1.4 0 5 10 15 20 25 1.2 1.1 TYPE D FULL DRIVE COMP (RISE) y = 0.0007x + 1.0964 1.0 30 0.8 35 TYPE D HALF DRIVE COMP (RISE) y = 0.0031x + 1.1599 TYPE D FULL DRIVE TRUE (RISE & FALL) TYPE D FULL DRIVE COMP (FALL) y = 0.0008x + 1.1074 0.
ADSP-21469 Values of JB are provided for package comparison and PCB design considerations. Note that the thermal characteristics values provided in Table 56 are modeled values. Table 56. Thermal Characteristics for 324-Lead CSP_BGA Parameter JA JMA JMA JC JT JMT JMT Condition Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Typical 22.7 20.4 19.5 6.6 0.11 0.19 0.
ADSP-21469 CSP_BGA BALL ASSIGNMENT—AUTOMOTIVE MODELS Table 58 lists the automotive CSP_BGA ball assignments by signal. Table 58.
ADSP-21469 Table 58. CSP_BGA Ball Assignment (Alphabetical by Signal) (Continued) Signal GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball No.
ADSP-21469 A1 CORNER INDEX AREA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 A B D C D D D E D D F D D R D R D D D D G H D D D D A S J K L M T N P R T U V V D VDD_DDR2 VDD_EXT R VREF GND T VDD_THD I/O SIGNALS A VDD_A DD_INT S AGND Figure 58. Ball Configuration, Automotive Model Rev.
ADSP-21469 CSP_BGA BALL ASSIGNMENT—STANDARD MODELS Table 59 lists the standard model CSP_BGA ball assignments by signal. Table 59.
ADSP-21469 Table 59. CSP_BGA Ball Assignment (Alphabetical by Signal) (Continued) Signal GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball No.
ADSP-21469 A1 CORNER INDEX AREA 1 2 3 4 D R 5 6 7 8 9 10 11 12 13 14 15 16 17 18 A B D C D D E D D F D D D R D D D D G H D D D D A S J K L M T N P R T U V V D VDD_DDR2 VDD_EXT R VREF GND T VDD_THD NC A VDD_A I/O SIGNALS S AGND DD_INT Figure 59. Ball Configuration, Standard Model Rev.
ADSP-21469 OUTLINE DIMENSIONS The ADSP-21469 processor is available in a 19 mm by 19 mm CSP_BGA lead-free package. A1 BALL CORNER 19.10 19.00 SQ 18.90 A1 BALL CORNER 18 16 14 12 10 8 6 4 2 17 15 13 11 9 7 5 3 1 A B C D E F 17.00 BSC SQ G H J K L M 1.00 BSC N P R T U V 1.00 REF TOP VIEW *1.80 1.71 1.56 BOTTOM VIEW DETAIL A DETAIL A 1.31 1.21 1.11 0.50 NOM 0.45 MIN SEATING PLANE 0.70 COPLANARITY 0.60 0.20 0.
ADSP-21469 AUTOMOTIVE PRODUCTS The ADSP-21469W model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that automotive models may have specifications that differ from commercial models and designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown in Table 60 are available for use in automotive applications.
ADSP-21469 Rev.
ADSP-21469 ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07900-0-6/10(0) Rev.
