Blackfin Embedded Processor ADSP-BF504/ADSP-BF504F/ADSP-BF506F FEATURES PERIPHERALS Up to 400 MHz high performance Blackfin processor Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register and instruction model for ease of programming and compiler-friendly support Advanced debug, trace, and performance monitoring Accepts a range of supply voltages for internal and I/O operations.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F TABLE OF CONTENTS General Description ................................................. 3 ADSP-BF50x Voltage Regulation ............................ 15 Portable Low-Power Architecture ............................. 3 Clock Signals ...................................................... 15 System Integration ................................................ 3 Booting Modes ................................................... 16 Processor Peripherals ......................
ADSP-BF504/ADSP-BF504F/ADSP-BF506F GENERAL DESCRIPTION The ADSP-BF50x processors are members of the Blackfin® family of products, incorporating the Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin processors combine a dualMAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F BLACKFIN PROCESSOR CORE and 8-bit subtract/absolute value/accumulate (SAA) operations. Also provided are the compare/select and vector search instructions. As shown in Figure 2, the Blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs, and a 40-bit shifter. The computation units process 8-, 16-, or 32-bit data from the register file.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F The second core-accessible memory block is the L1 data memory, consisting of 32K bytes of SRAM, of which 16K bytes may be configured as cache. This memory block is accessed at full processor speed. The third memory block is 4K bytes of scratchpad SRAM, which runs at the same speed as the L1 memories, but this memory is only accessible as data SRAM and cannot be configured as cache memory.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F Booting The processor contains a small on-chip boot kernel, which configures the appropriate peripheral for booting. If the processor is configured to boot from boot ROM memory space, the processor starts executing from the on-chip boot ROM. For more information, see Booting Modes on Page 16. Event Handling The event controller on the processor handles all asynchronous and synchronous events to the processor.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F Table 3.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F Table 3.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F FLASH MEMORY The ADSP-BF504F and ADSP-BF506F processors include an on-chip 32M bit (×16, multiple bank, burst) Flash memory. The features of this memory include: • Synchronous/asynchronous read implementation of interleaved data streams. This feature is especially useful in video applications where data can be deinterleaved on the fly.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F The timers can generate interrupts to the processor core providing periodic events for synchronization, either to the system clock or to a count of external signals. In addition to the eight general-purpose programmable timers, a ninth timer is also provided. This extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generation of operating system periodic interrupts.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F • DMA operations with single-cycle overhead—Each SPORT can automatically receive and transmit multiple buffers of memory data. The processor can link or chain sequences of DMA transfers between a SPORT and memory. support for five to eight data bits; one or two stop bits; and none, even, or odd parity. Each UART port supports two modes of operation: • PIO (programmed I/O). The processor sends or receives data by writing or reading I/O-mapped UART registers.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F The PPI supports a variety of general-purpose and ITU-R 656 modes of operation. In general-purpose mode, the PPI provides half-duplex, bidirectional data transfer with up to 16 bits of data. Up to three frame synchronization signals are also provided. In ITU-R 656 mode, the PPI provides half-duplex bidirectional transfer of 8- or 10-bit video data. Additionally, on-chip decode of embedded start-of-line (SOL) and start-offield (SOF) preamble packets is supported.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F Each mailbox consists of eight 16-bit data words. The data is divided into fields, which includes a message identifier, a time stamp, a byte count, up to 8 bytes of data, and several control bits. Each node monitors the messages being passed on the network.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F In the active mode, it is possible to disable the control input to the PLL by setting the PLL_OFF bit in the PLL control register. This register can be accessed with a user-callable routine in the on-chip ROM called bfrom_SysControl(). If disabled, the PLL control input must be re-enabled before transitioning to the full-on or sleep modes. Table 4.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F specified by the crystal manufacturer. The user should verify the customized values based on careful investigations on multiple devices over temperature range. % Power Savings = ( 1 – Power Savings Factor ) × 100% where the variables in the equations are: A third-overtone crystal can be used for frequencies above 25 MHz. The circuit is then modified to ensure crystal operation only at the third overtone by adding a tuned inductor circuit as shown in Figure 4.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F “FINE” ADJUSTMENT REQUIRES PLL SEQUENCING PLL 0.5u to 64u CLKIN BOOTING MODES “COARSE” ADJUSTMENT ON-THE-FLY ÷ 1, 2, 4, 8 CCLK ÷ 1 to 15 SCLK The processor has several mechanisms (listed in Table 8) for automatically loading internal and external memory after a reset. The boot mode is defined by the BMODE input pins dedicated to this purpose. There are two categories of boot modes.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F • Boot from serial SPI memory, EEPROM or flash (BMODE = 0x3)—8-, 16-, 24-, or 32-bit addressable devices are supported. The processor uses the PF13 GPIO pin to select a single SPI EEPROM/flash device (connected to the SPI0 interface) and submits a read command and successive address bytes (0x00) until a valid 8-, 16-, 24-, or 32-bit addressable device is detected. Pull-up resistors are required on the SPI0_SEL1 and MISO pins.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F JTAG Test Access Port (TAP) on each JTAG processor. The emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an operation has been completed by the emulator, the processor system is set running at full speed with no impact on system timing.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F • Pin-configurable analog inputs is necessary to read from both DOUT pins simultaneously. Figure 7 (ADC (Internal), ACM, and SPORT Connections) shows both DOUTA and DOUTB of the ADC connected to one of the processor’s serial ports.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F Additional highlights of the internal ADC include: • Two complete ADC functions allow simultaneous sampling and conversion of two channels—Each ADC has three fully/pseudo differential pairs, or six single-ended channels, as programmed. The conversion result of both channels is simultaneously available on separate data lines, or in succession on one data line if only one serial connection is available.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F SIGNAL DESCRIPTIONS Signal definitions for the ADSP-BF50x processors are listed in Table 11. All pins for the ADC (ADSP-BF506F processor only) are listed in Table 12. hibernate, all signals are three-stated with the following exceptions: EXT_WAKE is driven low and XTAL is driven to a solid logic level. In order to maintain maximum function and reduce package size and pin count, some pins have multiple, multiplexed functions.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F Table 11.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F Table 12. ADC—Signal Descriptions (ADSP-BF506F Processor Only) Signal Name DGND REF SELECT AVDD DCAPA, DCAPB (VREF) AGND VA1 to VA6 VB1 to VB6 RANGE SGL/DIFF A0 to A2 CS ADSCLK Type Function G Digital Ground. This is the ground reference point for all digital circuitry on the internal ADC. Both DGND pins should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F Table 12. ADC—Signal Descriptions (ADSP-BF506F Processor Only) (Continued) Signal Name DOUTA, DOUTB VDRIVE DVDD Type Function O Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on the falling edge of the ADSCLK input and 14 ADSCLKs are required to access the data. The data simultaneously appears on both pins from the simultaneous conversions of both ADCs.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F PROCESSOR—SPECIFICATIONS Specifications are subject to change without notice.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F ADSP-BF50x Clock Related Operating Conditions Table 14 describes the core clock timing requirements for the ADSP-BF50x processors. Take care in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock and system clock (see Table 16). Table 15 describes phaselocked loop operating conditions. Table 14.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F PROCESSOR—ELECTRICAL CHARACTERISTICS Parameter Test Conditions Min High Level Output Voltage VDDEXT = 1.7 V, IOH = –0.5 mA 1.35 High Level Output Voltage VDDEXT = 2.25 V, IOH = –0.5 mA 2.0 V High Level Output Voltage VDDEXT = 3.0 V, IOH = –0.5 mA V VOL Low Level Output Voltage VDDEXT = 1.7 V/2.25 V/3.0 V, IOL = 2.0 mA 0.4 V IIH High Level Input Current1 VDDEXT =3.6 V, VIN = 3.6 V 10.0 μA VDDEXT =3.6 V, VIN = 0 V 10.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F Parameter Test Conditions Min Typical Max Unit IDDFLASH2 Flash Memory Supply Current 2 — Reset/Powerdown 15 50 μA IDDFLASH3 Flash Memory Supply Current 3 — Standby 15 50 μA IDDFLASH4 Flash Memory Supply Current 4 — Automatic Standby 15 50 μA IDDFLASH5 Flash Memory Supply Current 5 — Program 15 40 mA Flash Memory Supply Current 5 — Erase 15 40 mA Program/Erase in one bank, asynchronous read in another bank 25 60 mA Program/Erase in one bank
ADSP-BF504/ADSP-BF504F/ADSP-BF506F Total Power Dissipation The ASF is combined with the CCLK Frequency and VDDINT dependent data in Table 19 to calculate this part. The second part is due to transistor switching in the system clock (SCLK) domain, which is included in the IDDINT specification equation. Total power dissipation has two components: 1. Static, including leakage current 2.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F PROCESSOR—ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in Table 20 may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 20.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F ESD SENSITIVITY PACKAGE INFORMATION ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F PROCESSOR—TIMING SPECIFICATIONS Specifications subject to change without notice. Clock and Reset Timing Table 24 and Figure 10 describe clock and reset operations. Per the CCLK and SCLK timing specifications in Table 14 to Table 16, combinations of CLKIN and clock multipliers must not select core/peripheral clocks in excess of the processor’s speed grade. Table 25 and Figure 11 describe clock out timing. Table 24.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F Table 25. Clock Out Timing Min Parameter Switching Characteristics tSCLK CLKOUT1 Period2,3 tSCLKH CLKOUT1 Width High tSCLKL CLKOUT1 Width Low VDDEXT = 1.8 V Max Min 10 4 4 VDDEXT = 2.5 V/3.3 V Max 10 4 4 Unit ns ns ns 1 The ADSP-BF504/ADSP-BF504F/ADSP-BF506F processor does not have a dedicated CLKOUT pin. Rather, the EXTCLK pin may be programmed to serve as CLKBUF or CLKOUT. This parameter applies when EXTCLK is programmed to output CLKOUT.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F Parallel Peripheral Interface Timing Table 27 and Figure 14 on Page 34, Figure 20 on Page 39, and Figure 22 on Page 40 describe parallel peripheral interface operations. Table 27.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F DATA DRIVEN / FRAME SYNC SAMPLED PPI_CLK tSFSPE tHFSPE tPCLKW tPCLK PPI_FS1/2 tDDTPE tHDTPE PPI_DATA Figure 15. PPI GP Tx Mode with External Frame Sync Timing FRAME SYNC DRIVEN DATA SAMPLED PPI_CLK tDFSPE tPCLKW tHOFSPE tPCLK PPI_FS1/2 tSDRPE tHDRPE PPI_DATA Figure 16. PPI GP Rx Mode with Internal Frame Sync Timing FRAME SYNC DRIVEN DATA DRIVEN tPCLK PPI_CLK tDFSPE tPCLKW tHOFSPE PPI_FS1/2 tDDTPE tHDTPE PPI_DATA Figure 17.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F RSI Controller Timing Table 28 and Figure 18 describe RSI Controller Timing. Table 29 and Figure 19 describe RSI controller (high speed) timing. Table 28.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F Table 29. RSI Controller Timing (High Speed Mode) Parameter Timing Requirements Input Setup Time tISU Input Hold Time tIH Switching Characteristics Clock Frequency Data Transfer Mode fPP1 Clock Low Time tWL Clock High Time tWH tTLH Clock Rise Time Clock Fall Time tTHL Output Delay Time During Data Transfer Mode tODLY tOH Output Hold Time 1 Min Max Unit 5.75 2 0 7 7 ns ns 50 MHz ns ns ns ns ns ns 3 3 2.5 2.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F Serial Ports Table 30 through Table 33 on Page 40 and Figure 20 on Page 39 through Figure 22 on Page 40 describe serial port operations. Table 30.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F DATA RECEIVE—INTERNAL CLOCK DATA RECEIVE—EXTERNAL CLOCK DRIVE EDGE DRIVE EDGE SAMPLE EDGE SAMPLE EDGE tSCLKE tSCLKEW tSCLKIW RSCLKx RSCLKx tDFSE tDFSI tHOFSI tHOFSE RFSx (OUTPUT) RFSx (OUTPUT) tSFSI tHFSI RFSx (INPUT) tSFSE tHFSE tSDRE tHDRE RFSx (INPUT) tSDRI tHDRI DRx DRx DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE DATA TRANSMIT—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE tSCLKIW SAMPLE EDGE t SCLKEW TSCLKx tSCLKE TSCLKx tD FSI tDFSE tHOFSI tH
ADSP-BF504/ADSP-BF504F/ADSP-BF506F Table 33. Serial Ports — External Late Frame Sync Min Parameter Switching Characteristics tDDTLFSE Data Delay from Late External TFSx or External RFSx in Multi-channel Mode With MFD = 01, 2 tDTENLFSE Data Enable from External RFSx in Multi-channel Mode With 0.0 MFD = 01, 2 1 2 VDDEXT = 1.8 V Max 12.0 DRIVE EDGE RSCLKx RFSx tDDTLFSE tDTENLFSE 1ST BIT DTx LATE EXTERNAL TFSx DRIVE EDGE SAMPLE EDGE DRIVE EDGE TSCLKx TFSx tDDTLFSE 1ST BIT DTx Figure 22.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F Serial Peripheral Interface (SPI) Port—Master Timing Table 34 and Figure 23 describe SPI port master operations. Table 34.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F Serial Peripheral Interface (SPI) Port—Slave Timing Table 35 and Figure 24 describe SPI port slave operations. Table 35.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing The UART ports receive and transmit operations are described in the ADSP-BF50x Hardware Reference Manual. General-Purpose Port Timing Table 36 and Figure 25 describe general-purpose port operations. Table 36.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F Timer Cycle Timing Table 37 and Figure 26 describe timer expired operations. The input signal is asynchronous in “width capture mode” and “external clock mode” and has an absolute maximum input frequency of (fSCLK/2) MHz. Table 37.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F Timer Clock Timing Table 38 and Figure 27 describe timer clock timing. Table 38. Timer Clock Timing Min Parameter Switching Characteristic tTODP Timer Output Update Delay After PPI_CLK High VDDEXT = 1.8 V Max Min VDDEXT = 2.5 V/3.3 V Max 12.0 12.0 Unit ns PPI_CLK tTODP TMRx OUTPUT Figure 27. Timer Clock Timing Up/Down Counter/Rotary Encoder Timing Table 39.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F Pulse Width Modulator (PWM) Timing Table 40 and Figure 29 describe PWM operations. Table 40.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F ADC Controller Module (ACM) Timing Table 41 and Figure 30 describe ACM operations. Note that the ACM clock (ACLK) frequency in MHz is set by the following equation (in which ACMCKDIV ranges from 0 to 255). 1 t ACLK = -------------f ACLK f SCLK f ACLK = -------------------------------------------------------( 2 × ACMCKDIV ) + 2 Table 41. ACM Timing VDDEXT = 1.8 V Parameter Min Max VDDEXT = 2.5 V/3.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F JTAG Test And Emulation Port Timing Table 42 and Figure 31 describe JTAG port operations. Table 42.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F PROCESSOR—OUTPUT DRIVE CURRENTS The curves represent the current drive capability of the output drivers. See Table 11 on Page 21 for information about which driver type corresponds to a particular ball. 120 240 VDDEXT = 3.6V @ – 55°C 200 VDDEXT = 3.3V @ 25°C 100 160 VDDEXT = 3.0V @ 125°C 80 120 VDDEXT = 3.6V @ – 55°C VDDEXT = 3.3V @ 25°C VDDEXT = 3.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F PROCESSOR—TEST CONDITIONS 0 VDDEXT = 3.6V @ – 55°C SOURCE CURRENT (mA) All timing parameters appearing in this data sheet were measured under the conditions described in this section. Figure 41 shows the measurement point for AC measurements (except output enable/disable). The measurement point VMEAS is VDDEXT/2 for VDDEXT (nominal) = 1.8 V/2.5 V/3.3 V. VDDEXT = 3.3V @ 25°C –10 VDDEXT = 3.0V @ 125°C –20 –30 VOL INPUT OR OUTPUT –40 VMEAS VMEAS –50 Figure 41.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F Output Disable Time Measurement 9 The time for the voltage on the bus to decay by ΔV is dependent on the capacitive load CL and the load current IL. This decay time can be approximated by the equation: 8 tRISE 7 RISE AND FALL TIME (ns) Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage.
RISE AND FALL TIME (ns) ADSP-BF504/ADSP-BF504F/ADSP-BF506F 25 PROCESSOR—ENVIRONMENTAL CONDITIONS 20 To determine the junction temperature on the application printed circuit board use: tRISE 15 T J = T CASE + ( Ψ JT × P D ) tFALL where: TJ = junction temperature (°C). 10 TCASE = case temperature (°C) measured by customer at top center of package. ΨJT = from Table 43 and Table 44. 5 tRISE = 1.8V @ 25°C tFALL = 1.8V @ 25°C 0 0 50 100 200 150 250 LOAD CAPACITANCE (pF) Figure 47.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F FLASH—SPECIFICATIONS Specifications subject to change without notice. FLASH—PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES The program and erase times and the number of program/ erase cycles per block are shown in Table 45. Exact erase times may change depending on the memory array condition. The best case is when all the bits in the block or bank are at ‘0’ (pre programmed). The worst case is when all the bits in the block or bank are at ‘1’ (not pre programmed).
ADSP-BF504/ADSP-BF504F/ADSP-BF506F ADC—SPECIFICATIONS Specifications are subject to change without notice. ADC—OPERATING CONDITIONS Parameter Conditions Min Max Unit VDD1 (AVDD, DVDD, VDRIVE) fADSCLK = 24 MHz, fS up to 1.5 MSPS, internal or external reference = 2.5 V ± 1% unless otherwise noted 2.7 3.6 V fADSCLK = 25 MHz, fS up to 1.56 MSPS, internal or external reference = 2.5 V ± 1% unless otherwise noted 3.0 3.6 V fADSCLK = 32 MHz, fS up to 2.0 MSPS, internal or external reference = 2.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F Table 47. Operating Conditions (Analog, Voltage Reference, and Logic I/O) (Continued) Parameter DIGITAL LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating State Leakage Current Floating State Output Capacitance4 Output Coding8 Specification Unit Test Conditions/Comments VDRIVE – 0.2 0.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F Table 48.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F ADC—TIMING SPECIFICATIONS Table 50. Serial Data Interface1 Parameter fADSCLK2 tCONVERT tQUIET t2 t3 t4 3 t5 t6 t7 t8 t9 t10 Specification 1/32 14 × tADSCLK 437.5 560.0 583.3 30 18/23 15 27/36 0.45 tADSCLK 0.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F ADC—TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. –60 INTERNAL REFERENCE 4096 POINT FFT VDD = 5V, VDRIVE = 3V FSAMPLE = 2MSPS FIN = 52kHz SINAD = 71.4dB THD = –84.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F 1.0 0.8 9000 POSITIVE DNL 0.4 POSITIVE INL 0.2 0 –0.2 NEGATIVE INL –0.4 –0.6 7000 6000 5000 4000 3000 1000 0 0.5 1.0 1.5 2.0 0 2046 2.5 2047 2048 Figure 56. Linearity Error vs. VREF 2050 Figure 59. Histogram of Codes for 10k Samples in Differential Mode 12.0 10000 11.5 9000 11.0 INTERNAL REFERENCE SINGLE-ENDED MODE 9984 CODES 8000 NO. OF OCCURRENCES VDD = 5V SINGLE-ENDED MODE 10.5 10.0 VDD = 3V SINGLE-ENDED MODE 9.5 9.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F ADC—TERMINOLOGY Negative Gain Error Match This is the difference in negative gain error across all 12 channels. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Integral Nonlinearity (INL) Integral nonlinearity is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F determining how much that signal is attenuated in the selected channel with a 50 kHz signal (0 V to VREF). The result obtained is the worst-case across all 12 channels for the ADC. Intermodulation Distortion (IMD) With inputs consisting of sine waves at two frequencies, fa and fb, any active device with non-linearities create distortion products at sum, and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, and so on.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F When the ADC starts a conversion (see Figure 63 (ADC Conversion Phase)), SW3 opens and SW1 and SW2 move to Position B, causing the comparator to become unbalanced. Both inputs are disconnected once the conversion begins. The control logic and the charge redistribution DACs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F +2.5V –60 FSAMPLE = 1.5MSPS VDD = 3V RANGE = 0V TO VREF –65 +1.25V 0V VIN RSOURCE = 100 VA1 ADC1 VREF R VB6 (DCAPA/DCAPB) –75 0.47μF –80 RSOURCE = 47 –85 1ADDITIONAL PINS OMITTED FOR CLARITY. RSOURCE = 10 –90 Figure 68. Single-Ended Mode Connection Diagram 0 100 200 300 400 500 600 700 INPUT FREQUENCY (kHz) 800 900 1000 Differential Mode Figure 66. THD vs.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F supply using the 0 to VREF range or 2 × VREF range, respectively. The common mode must be in this range to guarantee the functionality of the ADC. When a conversion takes place, the common mode is rejected, resulting in a virtually noise free signal of amplitude –VREF to +VREF corresponding to the digital codes of 0 to 4096. If the 2 × VREF range is used, then the input signal amplitude extends from – 2 VREF to +2 VREF after conversion. 3.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F 2 × VREF p–p 440 GND 3.75V 220 2.5 2.5V V+ TA = 25°C 1.25V 27 VIN+ ADC 1 2.0 V– 220 220 2.5V V+ VREF 1.25V 27 A 1.5 3.75V VIN– (V) 220k VIN– (DCAPA/DCAPB) V– 1.0 0.5 10k 0.47μF 20k 0 1ADDITIONAL PINS OMITTED FOR CLARITY. –0.5 0 Figure 73. Dual Op Amp Circuit to Convert a Single-Ended Bipolar Signal into a Differential Unipolar Signal 0.5 1.0 1.5 2.0 2.5 3.0 VREF (V) 3.5 4.0 4.5 5.0 Figure 75. VIN– Input Voltage Range vs.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F required acquisition time for the next sampling instant at Point B; therefore, the analog inputs are configured as differential for that conversion. altered after the third falling edge of ADSCLK. If this pin is tied to a logic low, the analog input range selected is 0 V to VREF. If this pin is tied to a logic high, the analog input range selected is 0 V to 2 × VREF.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F agement options. These options can be chosen to optimize the power dissipation/throughput rate ratio for differing application requirements. 111...111 ADC CODE 111...110 Normal Mode This mode is intended for applications needing fastest throughput rates because the user does not have to worry about any power-up times with the ADC remaining fully powered at all times. Figure 80 (Normal Mode Operation) shows the general diagram of the operation of the ADC in this mode.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F down for a relatively long duration between these bursts of several conversions. When the ADC is in partial power-down, all analog circuitry is powered down except for the on-chip reference and reference buffer. again on the rising edge of CS. If the ADC is already in partial power-down mode and CS is brought high between the second and 10th falling edges of ADSCLK, the device enters full powerdown mode.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F THE PART ENTERS PARTIAL POWER DOWN. THE PART BEGINS TO POWER UP. THE PART ENTERS FULL POWER DOWN. CS ADSCLK 1 2 DOUTA DOUTB 10 14 1 2 THREE-STATE INVALID DATA 10 INVALID DATA 14 THREE-STATE Figure 83. Entering Full Power-Down Mode THE PART BEGINS TO POWER UP. THE PART IS FULLY POWERED UP, SEE POWER-UP TIMES SECTION. tPOWER-UP2 CS ADSCLK DOUTA DOUTB 14 10 1 14 1 INVALID DATA VALID DATA Figure 84.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F maximum ADSCLK frequency and an ADSCLK frequency that scales with the sampling rate with VDD = 3 V and VDD = 5 V, respectively. In all cases, the internal reference was used. 10.0 Likewise, if CS is held low for a further 14 (or 16) ADSCLK cycles on DOUTB, the data from Conversion A is output on DOUTB. TA = 25°C 9.5 This is illustrated in Figure 88 (Reading Data from Both ADCs on One DOUT Line with 32 ADSCLKs) where the case for DOUTA is shown.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F CS t9 t2 ADSCLK t6 1 3 2 4 t3 DOUTA 0 DB11 0 DOUTB THREESTATE 2 LEADING ZEROS t4 DB10 B 5 13 t5 t7 DB9 DB2 DB8 tQUIET t8 DB1 DB0 THREE-STATE Figure 87. Serial Interface Timing Diagram CS t6 t2 ADSCLK 3 2 1 4 5 14 16 15 17 32 t5 t3 DOUTA t4 0 ZERO DB11A THREESTATE 2 LEADING ZEROS DB10A t10 t7 DB9A ZERO ZERO ZERO ZERO DB11B 2 TRAILING ZEROS 2 LEADING ZEROS Figure 88.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F 120-LEAD LQFP LEAD ASSIGNMENT Table 54 lists the LQFP leads by signal mnemonic. Table 55 on Page 73 lists the LQFP leads by lead number. Table 54. 120-Lead LQFP Lead Assignment (Alphabetical by Signal) Signal A0 A1 A2 AGND AGND AGND AGND AGND AGND AVDD BMODE0 BMODE1 BMODE2 CLKIN CS DCAPA DCAPB DGND DGND DOUTA DOUTB DVDD EMU EXT_WAKE EXTCLK GND GND GND GND NC Lead No.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F Table 55. 120-Lead LQFP Lead Assignment (Numerical by Lead Number) Lead No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Signal VDDEXT PF2 PF4 PF3 PF5 VDDEXT PF6 PF7 PF8 PF9 NMI RESET GND PF10 VDDEXT PF11 GND PF12 PF13 VDDEXT PF14 PF15 VDDEXT VDDINT VDDFLASH VDDEXT PG0 PG1 PG2 VDDEXT Lead No.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F Figure 89 shows the top view of the 120-lead LQFP package lead configuration. PIN 120 Figure 90 shows the bottom view of the 120-lead LQFP package lead configuration. PIN 91 PIN 1 PIN 31 PIN 90 PIN 1 INDICATOR PIN 60 PIN 30 120-LEAD LQFP TOP VIEW PIN 61 GND PAD (PIN 121) 120-LEAD LQFP BOTTOM VIEW AGND PAD (PIN 122) PIN 30 PIN 61 PIN 31 PIN 1 PIN 60 PIN 90 PIN 120 Figure 89. 120-Lead LQFP Package Lead Configuration (Top View) Rev. A | PIN 91 Figure 90.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F 88-LEAD LFCSP LEAD ASSIGNMENT Table 56 lists the LFCSP leads by signal mnemonic. Table 57 on Page 76 lists the LFCSP by lead number. Table 56. 88-Lead LFCSP Lead Assignment (Alphabetical by Signal) Signal BMODE0 BMODE1 BMODE2 CLKIN EMU EXT_WAKE EXTCLK GND GND GND NC NC NC NC NC NC NC NMI PF0 PF1 PF2 PF3 Lead No.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F Table 57. 88-Lead LFCSP Lead Assignment (Numerical by Lead Number) Lead No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Signal NMI RESET GND PF10 VDDEXT PF11 GND PF12 PF13 VDDEXT PF14 PF15 VDDEXT VDDINT VDDFLASH VDDEXT PG0 PG1 PG2 VDDEXT PG3 PG4 Lead No. 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Signal TDI TCK TMS TRST TDO PG5 PG6 PG7 VDDEXT VDDINT PG8 PG9 PG10 PG11 PG12 PG13 PG14 PG15 VDDEXT VDDINT SDA SCL Lead No.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F Figure 91 shows the top view of the LFCSP pin configuration. PIN 88 Figure 92 shows the bottom view of the LFCSP lead configuration. PIN 67 PIN 1 PIN 67 PIN 66 PIN 1 INDICATOR PIN 66 PIN 1 88-LEAD LFCSP BOTTOM VIEW 88-LEAD LFCSP TOP VIEW GND PAD (PIN 89) PIN 22 PIN 45 PIN 23 PIN 88 PIN 45 PIN 44 PIN 22 PIN 46 Figure 91. 88-Lead LFCSP Lead Configuration (Top View) Rev. A | PIN 1 INDICATOR PIN 23 Figure 92.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F OUTLINE DIMENSIONS Dimensions in Figure 93 (for the 120-lead LQFP) and in Figure 94 (for the 88-lead LFCSP) are shown in millimeters. 16.20 16.00 SQ 15.80 14.10 14.00 SQ 13.90 91 120 1 1.60 MAX 0.75 0.60 0.45 90 0.23 0.18 0.13 PIN 1 1.00 REF VIEW A 12° 1.45 1.40 1.35 0.15 0.10 0.05 0.20 0.15 0.09 7° 0° SEATING PLANE 0.40 BSC LEAD PITCH TOP VIEW (PINS DOWN) 30 61 31 0.08 MAX COPLANARITY 60 4.60 REF VIEW A 0.77 REF 1.53 31 60 61 30 6.17 REF 1.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F 12.10 12.00 SQ 11.90 0.60 MAX 0.60 MAX 88 67 66 PIN 1 INDICATOR 1 PIN 1 INDICATOR 11.85 11.75 SQ 11.65 0.50 BSC 0.50 0.40 0.30 45 44 SEATING PLANE 0.30 0.23 0.18 0.045 0.025 0.005 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE LEAD ASSIGNMENT AND SIGNAL DESCRIPTIONS SECTIONS OF THIS DATA SHEET. 0.138~0.194 REF Figure 94.
ADSP-BF504/ADSP-BF504F/ADSP-BF506F AUTOMOTIVE PRODUCTS The ADBF504W model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models and designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown in Table 58 are available for use in automotive applications.
