Blackfin Embedded Processor ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 FEATURES PERIPHERALS Up to 600 MHz high performance Blackfin processor Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register and instruction model for ease of programming and compiler-friendly support Advanced debug, trace, and performance monitoring Accepts a wide range of supply voltages for internal and I/O operations.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 TABLE OF CONTENTS Features ................................................................. 1 Clock Signals ...................................................... 16 Memory ................................................................ 1 Booting Modes ................................................... 18 Peripherals ............................................................. 1 Instruction Set Description ...........................
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 GENERAL DESCRIPTION The ADSP-BF52x processors are members of the Blackfin family of products, incorporating the Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin® processors combine a dual-MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 BLACKFIN PROCESSOR CORE The compute register file contains eight 32-bit registers. When performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. All operands for compute operations come from the multiported register file and instruction constant fields.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 In addition, multiple L1 memory blocks are provided, offering a configurable mix of SRAM and cache. The memory management unit (MMU) provides memory protection for individual tasks that may be operating on the core and can protect system registers from unintended access. The architecture provides three modes of operation: user mode, supervisor mode, and emulation mode.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 The SDRAM controller can be programmed to interface to up to 128M bytes of SDRAM. A separate row can be open for each SDRAM internal bank and the SDRAM controller supports up to 4 internal SDRAM banks, improving overall performance. The asynchronous memory controller can be programmed to control up to four banks of devices with very flexible timing requirements for a wide variety of devices.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 controller to prioritize and control all system events. Conceptually, interrupts from the peripherals enter into the SIC and are then routed directly into the general-purpose interrupts of the CEC. Core Event Controller (CEC) The CEC supports nine general-purpose interrupts (IVG15–7), in addition to the dedicated interrupt and exception events.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 3.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 unmasked and is processed by the system when asserted. A cleared bit in the register masks the peripheral event, preventing the processor from servicing the event. Examples of DMA types supported by the processor DMA controller include: • A single, linear buffer that stops upon completion.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error. components as shown in Figure 4. RTXO RTXI If configured to generate a hardware reset, the watchdog timer resets both the core and the processor peripherals.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 • Bidirectional operation — Each SPORT has two sets of independent transmit and receive pins, enabling eight channels of I2S stereo audio. The SPI port’s clock rate is calculated as: • Buffered (8-deep) transmit and receive ports — Each port has a data register for transferring data words to and from other processor components and shift registers for shifting data in and out of the data registers.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 TWI CONTROLLER INTERFACE The processors include a 2-wire interface (TWI) module for providing a simple exchange method of control data between multiple devices. The TWI is compatible with the widely used I2C® bus standard. The TWI module offers the capabilities of simultaneous master and slave operation and support for both 7-bit addressing and multimedia data arbitration.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Each general-purpose port pin can be individually controlled by manipulation of the port control, status, and interrupt registers: • GPIO direction control register — Specifies the direction of each individual GPIO pin as input or output.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Entire Field Mode DYNAMIC POWER MANAGEMENT In this mode, the entire incoming bit stream is read in through the PPI. This includes active video, control preamble sequences, and ancillary data that may be embedded in horizontal and vertical blanking intervals. Data transfer starts immediately after synchronization to Field 1.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 System DMA access to L1 memory is not supported in sleep mode. Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings The deep sleep mode maximizes dynamic power savings by disabling the clocks to the processor core (CCLK) and to all synchronous peripherals (SCLK). Asynchronous peripherals, such as the RTC, may still be running but cannot access internal resources or external memory.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 ADSP-BF523/ADSP-BF525/ADSP-BF527 VOLTAGE REGULATION The ADSP-BF523/ADSP-BF525/ADSP-BF527 provides an onchip voltage regulator that can generate processor core voltage levels from an external supply. Figure 5 shows the typical external components required to complete the power management system. 2.25V TO 3.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 specified by the crystal manufacturer. The user should verify the customized values based on careful investigations on multiple devices over temperature range. BLACKFIN permitted to run up to the frequency specified by the part’s maximum instruction rate. The CLKOUT pin reflects the SCLK frequency to the off-chip world. It is part of the SDRAM interface, but it functions as a reference signal in other timing specifications as well.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 The maximum CCLK frequency not only depends on the part's maximum instruction rate (see Page 88). This frequency also depends on the applied VDDINT voltage. See Table 12 and Table 15 for details. The maximal system clock rate (SCLK) depends on the chip package and the applied VDDINT, VDDEXT, and VDDMEM voltages (see Table 14 and Table 17).
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 version 2.1. An I2C multiplexer can be used to select one processor at a time when booting multiple processors from a single TWI. • Boot from UART0 host on Port G (BMODE = 0x7) — Using an autobaud handshake sequence, a boot-stream formatted program is downloaded by the host. The host selects a bit rate within the UART clocking capabilities.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 signal. When using HWAIT, the host must still check ALLOW_CONFIG at least once before beginning to configure the Host DMA Port. After completing the configuration, the host is required to poll the READY bit in HOST_STATUS before beginning to transfer data. When the host sends an HIRQ control command, the boot kernel issues a CALL instruction to address 0xFFA0 0000.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 The other Analog Devices IDE, VisualDSP++, supports processor families introduced prior to the release of CrossCore Embedded Studio. This IDE includes the Analog Devices VDK real time operating system and an open source TCP/IP stack. For more information visit www.analog.com/visualdsp. Note that VisualDSP++ will not support future Analog Devices processors.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 RELATED SIGNAL CHAINS A signal chain is a series of signal-conditioning electronic components that receive input (data acquired from sampling either real-time phenomena or from stored data) in tandem, with the output of one portion of the chain supplying input to the next. Signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 SIGNAL DESCRIPTIONS Signal definitions for the ADSP-BF52x processors are listed in Table 10. In order to maintain maximum function and reduce package size and ball count, some balls have dual, multiplexed functions. In cases where ball function is reconfigurable, the default state is shown in plain text, while the alternate function is shown in italics.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 10. Signal Descriptions (Continued) Signal Name Type Function Driver Type1 USB 2.0 HS OTG USB_DP I/O Data + (This ball should be pulled low when USB is unused or not present.) F USB_DM I/O Data – (This ball should be pulled low when USB is unused or not present.) F USB_XI I USB Crystal Input (This ball should be pulled low when USB is unused or not present.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 10.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 10. Signal Descriptions (Continued) Type Function Driver Type1 I/O PPI Frame Sync1/Timer0 C PJ1: PPI_CLK/TMRCLK I PPI Clock/Timer Clock PJ2: SCL I/O 5V TWI Serial Clock (This pin is an open-drain output and requires a pull-up resistor.4) E PJ3: SDA I/O 5V TWI Serial Data (This pin is an open-drain output and requires a pull-up resistor.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 10. Signal Descriptions (Continued) Signal Name Type Function Driver Type1 ALL SUPPLIES MUST BE POWERED See Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors on Page 30, and see Operating Conditions for ADSP-BF522/ ADSP-BF524/ADSP-BF526 Processors on Page 28. Power Supplies VDDEXT P I/O Power Supply VDDINT P Internal Power Supply VDDRTC P Real Time Clock Power Supply VDDUSB P 3.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 SPECIFICATIONS Specifications are subject to change without notice.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 11 shows settings for TWI_DT in the NONGPIO_DRIVE register. Set this register prior to using the TWI port. Table 11. TWI_DT Field Selections and VDDEXT/VBUSTWI TWI_DT 000 (default)1 001 010 011 100 101 110 111 (reserved) 1 VDDEXT Nominal 3.3 1.8 2.5 1.8 3.3 1.8 2.5 – VBUSTWI Min 2.97 1.7 2.97 2.97 4.5 2.25 2.25 – VBUSTWI Nominal 3.3 1.8 3.3 3.3 5 2.5 2.5 – VBUSTWI Max 3.63 1.98 3.63 3.63 5.5 2.75 2.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 OPERATING CONDITIONS FOR ADSP-BF523/ADSP-BF525/ADSP-BF527 PROCESSORS Parameter VDDINT VDDINT Internal Supply Voltage1 Internal Supply Voltage1 VDDINT VDDEXT Internal Supply Voltage1 External Supply Voltage4, 5 VDDEXT VDDEXT VDDEXT VDDRTC VDDRTC VDDMEM VDDMEM VDDMEM VDDMEM VDDOTP VPPOTP VDDUSB VIH VIH VIH VIHTWI VIL VIL VIL VILTWI TJ External Supply Voltage4, 5 External Supply Voltage4, 5 External Supply Voltage4, 5 RTC Power Supply Volta
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Clock Related Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Table 15 describes the core clock timing requirements for the ADSP-BF523/ADSP-BF525/ADSP-BF527 processors. Take care in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock and system clock (see Table 17). Table 16 describes phase-locked loop operating conditions.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 ELECTRICAL CHARACTERISTICS Table 18. Common Electrical Characteristics for All ADSP-BF52x Processors Parameter Test Conditions Min Typical Max Unit VOH High Level Output Voltage VDDEXT /VDDMEM = 1.7 V, IOH = –0.5 mA 1.35 V VOH High Level Output Voltage VDDEXT /VDDMEM = 2.25 V, IOH = –0.5 mA 2.0 V VOH High Level Output Voltage VDDEXT /VDDMEM = 3.0 V, IOH = –0.5 mA 2.4 V VOL Low Level Output Voltage VDDEXT /VDDMEM = 1.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 19. Electrical Characteristics for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors Parameter 1 Test Conditions Min Typical Max Unit VDDINT Current in VDDINT = 1.3 V, fCCLK = 0 MHz, fSCLK = 0 MHz, Deep Sleep Mode TJ = 25°C, ASF = 0.00 2 mA IDDSLEEP VDDINT Current in Sleep Mode VDDINT = 1.3 V, fSCLK = 25 MHz, TJ = 25°C 13 mA IDD-IDLE VDDINT Current in Idle VDDINT = 1.3 V, fCCLK = 300 MHz, fSCLK = 25 MHz, TJ = 25°C, ASF = 0.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 20. Electrical Characteristics for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Parameter 1 Test Conditions Min Typical Max Unit VDDINT Current in VDDINT = 1.0 V, fCCLK = 0 MHz, fSCLK = 0 MHz, Deep Sleep Mode TJ = 25°C, ASF = 0.00 10 mA IDDSLEEP VDDINT Current in Sleep Mode VDDINT = 1.0 V, fSCLK = 25 MHz, TJ = 25°C 20 mA IDD-IDLE VDDINT Current in Idle VDDINT = 1.0 V, fCCLK = 400 MHz, fSCLK = 25 MHz, TJ = 25°C, ASF = 0.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Total Power Dissipation Total power dissipation has two components: 1. Static, including leakage current 2. Dynamic, due to transistor switching characteristics Many operating conditions can also affect power dissipation, including temperature, voltage, operating frequency, and processor activity. Electrical Characteristics on Page 32 shows the current dissipation for internal circuitry (VDDINT).
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 24. Static Current — IDD-DEEPSLEEP (mA) for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors 1 TJ (°C) –40 –20 0 25 40 55 70 85 100 105 115 125 1 0.95 V 6.5 9.0 13.2 22.3 30.8 42.9 59.1 80.4 109.3 120.8 144.4 173.9 1.00 V 7.8 10.6 15.2 25.4 34.8 47.9 65.6 88.6 118.7 132.1 157.5 189.1 Voltage (VDDINT)1 1.10 V 1.15 V 11.1 13.1 14.6 17.0 20.4 23.5 32.8 37.2 44.1 49.6 59.9 66.9 80.8 89.7 107.8 119.2 143.2 157.4 158.8 174.2 188.4 206.0 224.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in Table 26 may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other condi- tions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 26.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 PACKAGE INFORMATION Table 28. Total Current Pin Groups (Continued) Group 6 7 8 9 10 11 12 13 14 15 16 17 18 The information presented in Figure 8 and Table 31 provides details about the package branding for the ADSP-BF52x processors. For a complete listing of product availability, see Ordering Guide on Page 88.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 TIMING SPECIFICATIONS Specifications are subject to change without notice. Clock and Reset Timing Table 32 and Figure 9 describe clock and reset operations. Per the CCLK and SCLK timing specifications in Table 12 to Table 17, combinations of CLKIN and clock multipliers must not select core/peripheral clocks in excess of the processor's maximum instruction rate. Table 32.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 33. Power-Up Reset Timing Parameter Min Max Unit Timing Requirement tRST_IN_PWR RESET Deasserted after the VDDINT, VDDEXT, VDDRTC, VDDUSB, VDDMEM, VDDOTP, and CLKIN 3500 × tCKIN Pins are Stable and Within Specification tRST_IN_PWR RESET CLKIN V DD_SUPPLIES In Figure 10, VDD_SUPPLIES is VDDINT, VDDEXT, VDDRTC, VDDUSB, VDDMEM, and VDDOTP. Figure 10. Power-Up Reset Timing Rev.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Asynchronous Memory Read Cycle Timing Table 34. Asynchronous Memory Read Cycle Timing Parameter Timing Requirements tSDAT DATA15–0 Setup Before CLKOUT tHDAT DATA15–0 Hold After CLKOUT tSARDY ARDY Setup Before CLKOUT tHARDY ARDY Hold After CLKOUT Switching Characteristics tDO Output Delay After CLKOUT1 tHO Output Hold After CLKOUT1 1 ADSP-BF522/ADSP-BF524/ ADSP-BF526 VDDMEM VDDMEM 1.8 V Nominal 2.5 V or 3.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Asynchronous Memory Write Cycle Timing Table 35. Asynchronous Memory Write Cycle Timing ADSP-BF522/ADSP-BF524/ ADSP-BF526 VDDMEM 1.8 V Nominal Parameter Min Max ADSP-BF523/ADSP-BF525/ ADSP-BF527 VDDMEM 2.5 V or 3.3 V Nominal Min Max VDDMEM 1.8 V Nominal Min Max VDDMEM 2.5 V or 3.3 V Nominal Min Max Unit Timing Requirements tSARDY ARDY Setup Before CLKOUT 4.0 4.0 4.0 4.0 ns tHARDY ARDY Hold After CLKOUT 0.2 0.2 0.2 0.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 NAND Flash Controller Interface Timing Table 36 and Figure 13 on Page 44 through Figure 17 on Page 46 describe NAND Flash Controller Interface operations. Table 36. NAND Flash Controller Interface Timing VDDEXT 1.8 V Nominal Parameter VDDEXT 2.5 V or 3.3 V Nominal Min Min Unit ns Write Cycle Switching Characteristics tCWL ND_CE Setup Time to AWE Low 1.0 × tSCLK – 4 1.0 × tSCLK – 4 tCH ND_CE Hold Time From AWE High 3.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 tCWL tCH ND_CE ND_CLE tCLEWL tCLH tALEWL tALH ND_ALE tWP AWE tDWH tDWS ND_DATA In Figure 13, ND_DATA is ND_D0–D7. Figure 13. NAND Flash Controller Interface Timing — Command Write Cycle tCWL ND_CE tCLEWL ND_CLE ND_ALE tALH tALEWL tALH tALEWL tWP tWHWL tWP AWE tWC tDWS tDWH tDWS ND_DATA In Figure 14, ND_DATA is ND_D0–D7. Figure 14. NAND Flash Controller Interface Timing — Address Write Cycle Rev.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 tCWL ND_CE tCLEWL ND_CLE tALEWL ND_ALE tWP tWC AWE tWP tDWS tWHWL tDWH tDWS tDWH ND_DATA In Figure 15, ND_DATA is ND_D0–D7. Figure 15. NAND Flash Controller Interface Timing — Data Write Operation tCRL tCRH ND_CE ND_CLE ND_ALE tRP tRC ARE tRHRL tRP tDRS tDRH tDRS ND_DATA In Figure 16, ND_DATA is ND_D0–D7. Figure 16. NAND Flash Controller Interface Timing — Data Read Operation Rev.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 tCLWL ND_CE ND_CLE tCLEWL tCLH tWP AWE tWHRL tRP ARE tDWS tDWH tDRS tDRH ND_DATA In Figure 17, ND_DATA is ND_D0–D7. Figure 17. NAND Flash Controller Interface Timing — Write Followed by Read Operation Rev.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 SDRAM Interface Timing Table 37. SDRAM Interface Timing for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors VDDMEM 1.8V Nominal Parameter Min Max VDDMEM 2.5 V or 3.3V Nominal Min Max Unit Timing Requirements tSSDAT Data Setup Before CLKOUT 1.5 1.5 ns tHSDAT Data Hold After CLKOUT 1.3 0.8 ns Switching Characteristics tSCLK CLKOUT Period1 12.5 10 ns tSCLKH CLKOUT Width High 5.0 4.0 ns tSCLKL CLKOUT Width Low 5.0 4.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 tSCLK CLKOUT tSSDAT tHSDAT tSCLKL tSCLKH DATA (IN) tENSDAT tDCAD tHCAD DATA (OUT) tDCAD tHCAD COMMAND, ADDRESS (OUT) NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE. Figure 18. SDRAM Interface Timing Rev.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 External DMA Request Timing Table 39, Table 40, and Figure 19 describe the External DMA Request operations. Table 39. External DMA Request Timing for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors1 VDDEXT/VDDMEM 1.8 V Nominal Parameter Min Max VDDEXT/VDDMEM 2.5 V or 3.3 V Nominal Min Max Unit Timing Requirements 1 tDS DMARx Asserted to CLKOUT High Setup 9.0 6.0 ns tDH CLKOUT High to DMARx Deasserted Hold Time 0.0 0.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Parallel Peripheral Interface Timing Table 41 and Figure 20 on Page 51, Figure 24 on Page 55, and Figure 27 on Page 57 describe parallel peripheral interface operations. Table 41. Parallel Peripheral Interface Timing for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors VDDEXT 1.8V Nominal Min Parameter Max VDDEXT 2.5 V or 3.3 V Nominal Min Max Unit Timing Requirements tPCLKW PPI_CLK Width1 6.4 6.4 ns tPCLK PPI_CLK Period1 25.0 20.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 DATA SAMPLED / FRAME SYNC SAMPLED DATA SAMPLED / FRAME SYNC SAMPLED PPI_CLK tSFSPE tPCLKW tHFSPE tPCLK PPI_FS1/2 tSDRPE tHDRPE PPI_DATA Figure 20. PPI GP Rx Mode with External Frame Sync Timing DATA DRIVEN / FRAME SYNC SAMPLED PPI_CLK tSFSPE tHFSPE tPCLKW PPI_FS1/2 tDDTPE tHDTPE PPI_DATA Figure 21.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 FRAME SYNC DRIVEN DATA DRIVEN tPCLK PPI_CLK tHOFSPE tDFSPE tPCLKW PPI_FS1/2 tDDTPE PPI_DATA Figure 23. PPI GP Tx Mode with Internal Frame Sync Timing Rev.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Serial Ports Table 43 through Table 47 on Page 57 and Figure 24 on Page 55 through Figure 27 on Page 57 describe serial port operations. Table 43. Serial Ports—External Clock ADSP-BF522/ADSP-BF524/ ADSP-BF526 VDDEXT 2.5 V or 3.3V Nominal VDDEXT 1.8V Nominal Parameter Min Max Min Max ADSP-BF523/ADSP-BF525/ ADSP-BF527 VDDEXT 2.5 V or 3.3V Nominal VDDEXT 1.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 44. Serial Ports—Internal Clock for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors VDDEXT 1.8V Nominal Min Parameter VDDEXT 2.5 V or 3.3V Nominal Max Min Max Unit Timing Requirements tSFSI TFSx/RFSx Setup Before TSCLKx/RSCLKx1 11.0 9.6 ns tHFSI TFSx/RFSx Hold After TSCLKx/RSCLKx1 –1.5 –1.5 ns 11.0 9.6 ns –1.5 –1.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 DATA RECEIVE—INTERNAL CLOCK DATA RECEIVE—EXTERNAL CLOCK DRIVE EDGE DRIVE EDGE SAMPLE EDGE SAMPLE EDGE tSCLKE tSCLKEW tSCLKIW RSCLKx RSCLKx tDFSE tDFSI tHOFSI tHOFSE RFSx (OUTPUT) RFSx (OUTPUT) tSFSI tHFSI RFSx (INPUT) tSFSE tHFSE tSDRE tHDRE RFSx (INPUT) tSDRI tHDRI DRx DRx DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE DATA TRANSMIT—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE tSCLKIW SAMPLE EDGE t SCLKEW TSCLKx tSCLKE TS
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 46. Serial Ports—Enable and Three-State ADSP-BF522/ADSP-BF524/ADSP-BF526 VDDEXT 1.8V Nominal Min Parameter Max VDDEXT 2.5 V or 3.3V Nominal Min Max ADSP-BF523/ADSP-BF525/ADSP-BF527 VDDEXT 1.8V Nominal Min Max VDDEXT 2.5 V or 3.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 47. Serial Ports — External Late Frame Sync ADSP-BF522/ADSP-BF524/ ADSP-BF526 VDDEXT 2.5 V or 3.3V Nominal VDDEXT 1.8V Nominal Min Parameter Max Min Max ADSP-BF523/ADSP-BF525/ ADSP-BF527 VDDEXT 2.5 V or 3.3V Nominal VDDEXT 1.8V Nominal Min Max Min Max Unit 10.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Serial Peripheral Interface (SPI) Port—Master Timing Table 48 and Figure 28 describe SPI port master operations. Table 48. Serial Peripheral Interface (SPI) Port—Master Timing ADSP-BF522/ADSP-BF524/ ADSP-BF526 VDDEXT 2.5 V or 3.3V Nominal VDDEXT 1.8V Nominal Min Parameter Max ADSP-BF523/ADSP-BF525/ ADSP-BF527 Min VDDEXT 2.5 V or 3.3V Nominal VDDEXT 1.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Serial Peripheral Interface (SPI) Port—Slave Timing Table 49 and Figure 29 describe SPI port slave operations. Table 49. Serial Peripheral Interface (SPI) Port—Slave Timing ADSP-BF522/ADSP-BF524/ ADSP-BF526 VDDEXT 2.5 V or 3.3V Nominal VDDEXT 1.8V Nominal Min Parameter ADSP-BF523/ADSP-BF525/ ADSP-BF527 Max Min VDDEXT 2.5 V or 3.3V Nominal VDDEXT 1.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing Table 50 describes the USB On-The-Go receive and transmit operations. Table 50. USB On-The-Go—Receive and Transmit Timing ADSP-BF522/ADSP-BF524/ADSP-BF526 VDDEXT 1.8V Nominal Parameter ADSP-BF523/ADSP-BF525/ ADSP-BF527 VDDEXT 1.8V Nominal VDDEXT 2.5 V or 3.3V Nominal VDDEXT 2.5 V or 3.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing For information on the UART port receive and transmit operations, see the ADSP-BF52x Hardware Reference Manual. General-Purpose Port Timing Table 51 and Figure 30 describe general-purpose port operations. Table 51. General-Purpose Port Timing for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors VDDEXT 1.8V Nominal Min Parameter Max VDDEXT 2.5 V or 3.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Timer Cycle Timing Table 53 and Figure 31 describe timer expired operations. The input signal is asynchronous in “width capture mode” and “external clock mode” and has an absolute maximum input frequency of (fSCLK/2) MHz. Table 53. Timer Cycle Timing ADSP-BF522/ADSP-BF524/ADSP-BF526 VDDEXT 1.8V Nominal Min Parameter ADSP-BF523/ADSP-BF525/ADSP-BF527 VDDEXT 1.8V Nominal VDDEXT 2.5 V or 3.3V Nominal Max Min Max Min Max VDDEXT 2.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Timer Clock Timing Table 54 and Figure 32 describe timer clock timing. Table 54. Timer Clock Timing VDDEXT 1.8V Nominal Min Parameter Max VDDEXT 2.5 V or 3.3V Nominal Min Max Unit 12.0 ns Switching Characteristic tTODP Timer Output Update Delay After PPI_CLK High 12.0 PPI_CLK tTODP TMRx OUTPUT Figure 32. Timer Clock Timing Up/Down Counter/Rotary Encoder Timing Table 55. Up/Down Counter/Rotary Encoder Timing VDDEXT 1.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 HOSTDP A/C Timing- Host Read Cycle Table 56 describes the HOSTDP A/C Host Read Cycle timing requirements. Table 56. Host Read Cycle Timing Requirements Parameter Timing Requirements tSADRDL HOST_ADDR and HOST_CE Setup before HOST_RD falling edge tHADRDH HOST_ADDR and HOST_CE Hold after HOST_RD rising edge tRDWL HOST_RD pulse width low (ACK mode) ADSP-BF522/ADSP-BF524/ ADSP-BF526 VDDEXT VDDEXT 2.5 V or 3.3V Nominal 1.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 HOST_ADDR HOST_CE tSADRDL tHADRDH tRDWL HOST_RD tSDATRDY tACC tRDWH tDDARWH tHDARWH HOST_DATA tDRDYRDL tDRDHRDY tRDYPRD HOST_ACK In Figure 34, HOST_DATA is HOST_D0–D15. Figure 34. HOSTDP A/C- Host Read Cycle Rev.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 HOSTDP A/C Timing- Host Write Cycle Table 57 describes the HOSTDP A/C Host Write Cycle timing requirements. Table 57. Host Write Cycle Timing Requirements Parameter Timing Requirements tSADWRL HOST_ADDR/HOST_CE Setup before HOST_WR falling edge tHADWRH HOST_ADDR/HOST_CE Hold after HOST_WR rising edge HOST_WR pulse width low tWRWL (ACK mode) ADSP-BF522/ADSP-BF524/ ADSP-BF526 VDDEXT 2.5 V or 3.3V VDDEXT Nominal 1.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 HOST_ADDR HOST_CE tSADWRL tHADWRH tWRWH tWRWL HOST_WR tSDATWH tHDATWH HOST_DATA tDRDYWRL tRDYPWR tDWRHRDY HOST_ACK In Figure 35, HOST_DATA is HOST_D0–D15. Figure 35. HOSTDP A/C- Host Write Cycle Rev.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 10/100 Ethernet MAC Controller Timing Table 58 through Table 63 and Figure 36 through Figure 41 describe the 10/100 Ethernet MAC Controller operations. Table 58. 10/100 Ethernet MAC Controller Timing: MII Receive Signal VDDEXT 1.8V Nominal Parameter1 VDDEXT 2.5 V or 3.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 60. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal VDDEXT 1.8V Nominal Parameter1 VDDEXT 2.5 V or 3.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 62. 10/100 Ethernet MAC Controller Timing: MII/RMII Asynchronous Signal VDDEXT 1.8V Nominal Min Parameter VDDEXT 2.5 V or 3.3V Nominal Max Min Max Unit Timing Requirements tECOLH COL Pulse Width High1 tETxCLK × 1.5 tERxCLK × 1.5 tETxCLK × 1.5 tERxCLK × 1.5 ns tECOLL COL Pulse Width Low1 tETxCLK × 1.5 tERxCLK × 1.5 tETxCLK × 1.5 tERxCLK × 1.5 ns tECRSH CRS Pulse Width High2 tETxCLK × 1.5 tETxCLK × 1.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 MDC (OUTPUT) tMDCOH MDIO (OUTPUT) tMDCOV MDIO (INPUT) tMDIOS tMDCIH Figure 41. 10/100 Ethernet MAC Controller Timing: MII Station Management Rev.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 JTAG Test And Emulation Port Timing Table 64 and Figure 42 describe JTAG port operations. Table 64. JTAG Port Timing VDDEXT 1.8V Nominal Min Parameter Max VDDEXT 2.5 V or 3.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 OUTPUT DRIVE CURRENTS Figure 43 through Figure 57 show typical current-voltage characteristics for the output drivers of the ADSP-BF52x processors. The curves represent the current drive capability of the output drivers. See Table 10 on Page 23 for information about which driver type corresponds to a particular ball. 200 160 240 200 VDDEXT = 3.0V @ 105°C 120 80 0 –40 –80 VOL –120 VDDEXT = 3.0V @ 105°C 120 VOH 40 VDDEXT = 3.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 100 160 120 VDDEXT = 3.3V @ 25°C 60 VDDEXT = 3.0V @ 105°C 40 VOH 20 0 –20 –40 VOL –60 VDDEXT = 3.3V @ 25°C VDDEXT = 3.0V @ 105°C 80 SOURCE CURRENT (mA) SOURCE CURRENT (mA) VDDEXT = 3.6V @ – 40°C VDDEXT = 3.6V @ – 40°C 80 VOH 40 0 –40 –80 VOL –120 –80 –100 –160 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 0.5 1.0 1.5 SOURCE VOLTAGE (V) Figure 49. Driver Type C Current (3.3V VDDEXT/VDDMEM) 3.0 3.5 120 VDDEXT = 2.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 TEST CONDITIONS 60 VDDEXT = 3.6V @ – 40°C 50 VDDEXT = 3.3V @ 25°C 40 VDDEXT = 3.0V @ 105°C SOURCE CURRENT (mA) 30 20 10 0 All Timing Requirements appearing in this data sheet were measured under the conditions described in this section. Figure 58 shows the measurement point for AC measurements (except output enable/disable). The measurement point VMEAS is VDDEXT/2 or VDDMEM/2 for VDDEXT/VDDMEM (nominal) = 1.8 V/ 2.5 V/3.3 V.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Output Disable Time Measurement TESTER PIN ELECTRONICS Output balls are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. The output disable time tDIS is the difference between tDIS_MEASURED and tDECAY as shown on the left side of Figure 59.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 7 7 6 tRISE 5 tFALL 4 3 2 1 tRISE = 2.5V @ 25°C RISE AND FALL TIME (10% TO 90%) RISE AND FALL TIME (10% TO 90%) 8 6 5 tRISE 4 tFALL 3 2 1 tRISE = 2.5V @ 25°C tFALL = 2.5V @ 25°C tFALL = 2.5V @ 25°C 0 0 50 100 0 200 150 0 50 LOAD CAPACITANCE (pF) 200 150 LOAD CAPACITANCE (pF) Figure 62. Driver Type A Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (2.5V VDDEXT/VDDMEM) Figure 65.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 10 9 14 12 tRISE 10 tFALL 8 6 4 2 tRISE = 2.5V @ 25°C RISE AND FALL TIME (10% TO 90%) RISE AND FALL TIME (10% TO 90%) 16 100 tFALL 5 4 3 2 tRISE = 2.5V @ 25°C tFALL = 2.5V @ 25°C 0 200 150 tRISE 6 0 0 50 7 1 tFALL = 2.5V @ 25°C 0 8 50 14 8 12 tRISE 10 8 tFALL 6 4 2 tRISE = 3.3V @ 25°C RISE AND FALL TIME (10% TO 90%) RISE AND FALL TIME (10% TO 90%) 200 150 Figure 71.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Values of JA are provided for package comparison and printed circuit board design considerations. JA can be used for a first order approximation of TJ by the equation: 9 RISE AND FALL TIME (10% TO 90%) 8 7 6 T J = T A + JA P D tRISE 5 tFALL where: 4 TA = Ambient temperature (°C) 3 2 tRISE = 2.5V @ 25°C 1 tFALL = 2.5V @ 25°C 0 0 50 100 200 150 LOAD CAPACITANCE (pF) Figure 74.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 289-BALL CSP_BGA BALL ASSIGNMENT Table 67 lists the CSP_BGA balls by signal mnemonic. Table 68 on Page 81 lists the CSP_BGA by ball number. Table 67. 289-Ball CSP_BGA Ball Assignment (Alphabetically by Signal) Ball Ball Ball Ball Ball Ball Ball Signal No. Signal No. Signal No. Signal No. Signal No. Signal No. Signal No.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 68. 289-Ball CSP_BGA Ball Assignment (Numerically by Ball Number) Ball Ball Ball Ball Ball Ball Ball No. Signal No. Signal No. Signal No. Signal No. Signal No. Signal No.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Figure 76 shows the top view of the BC-289-2 CSP_BGA ball configuration. Figure 77 shows the bottom view of the BC-289-2 CSP_BGA ball configuration. A1 BALL PAD CORNER A B C D E F G H J K L TOP VIEW M N P KEY: R V DDINT GND T NC U V V DDEXT I/O V W DDMEM Y AA AB AC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Figure 76.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 208-BALL CSP_BGA BALL ASSIGNMENT Table 69 lists the CSP_BGA balls by signal mnemonic. Table 70 on Page 84 lists the CSP_BGA by ball number. Table 69. 208-Ball CSP_BGA Ball Assignment (Alphabetically by Signal) Signal Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal Ball No.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 70. 208-Ball CSP_BGA Ball Assignment (Numerically by Ball Number) Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal Ball No.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Figure 78 shows the top view of the CSP_BGA ball configuration. Figure 79 shows the bottom view of the CSP_BGA ball configuration. A1 BALL PAD CORNER A B C D E F G H J K L M N P R T U V W Y TOP VIEW KEY: VDDINT GND VDDEXT I/O VDDMEM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Figure 78.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 OUTLINE DIMENSIONS Dimensions in the outline dimension figures (Figure 80 and Figure 81) are shown in millimeters. A1 BALL CORNER 12.00 BSC SQ 22 20 18 16 14 12 10 8 6 4 2 23 21 19 17 15 13 11 9 7 5 3 1 A C E G 11.00 BSC SQ J L N R 0.50 BSC U W B D F H K M P T V Y AA AB AC TOP VIEW BOTTOM VIEW DETAIL A 1.40 1.26 1.11 DETAIL A 0.20 MIN 0.35 COPLANARITY 0.08 0.30 0.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 SURFACE-MOUNT DESIGN Table 71 is provided as an aid to PCB design. For industry-standard design recommendations, refer to IPC-7351, Generic Requirements for Surface Mount Design and Land Pattern Standard. Table 71. Surface-Mount Design Supplement Package 289-Ball CSP_BGA 208-Ball CSP_BGA Package Ball Attach Type Solder Mask Defined Solder Mask Defined Package Solder Mask Opening 0.26 mm diameter 0.40 mm diameter Package Ball Pad Size 0.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 ORDERING GUIDE Model1 Temperature Range2 Instruction Rate (Max) Package Description Package Option ADSP-BF522BBCZ-3A –40°C to +85°C 300 MHz 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-208-2 ADSP-BF522BBCZ-4A –40°C to +85°C 400 MHz 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-208-2 ADSP-BF522KBCZ-3 0°C to +70°C 300 MHz 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-289-2 ADSP-BF522KBCZ-4