Blackfin Embedded Processor ADSP-BF538/ADSP-BF538F FEATURES PERIPHERALS Up to 533 MHz high performance Blackfin processor Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register and instruction model for ease of programming and compiler friendly support Advanced debug, trace, and performance monitoring Wide range of operating voltages (see Operating Conditions on Page 23) Programmable on-chip voltage regulator 316-ball Pb-free CSP_BGA package Parallel peripheral interfa
ADSP-BF538/ADSP-BF538F TABLE OF CONTENTS Features ................................................................. 1 Clock Signals ...................................................... 14 Memory ................................................................ 1 Booting Modes ................................................... 16 Peripherals ............................................................. 1 Instruction Set Description .................................... 16 General Description .........
ADSP-BF538/ADSP-BF538F GENERAL DESCRIPTION The ADSP-BF538/ADSP-BF538F processors are members of the Blackfin® family of products, incorporating the Analog Devices, Inc./Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual-MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction set architecture.
ADSP-BF538/ADSP-BF538F BLACKFIN PROCESSOR CORE instructions includes byte alignment and packing operations, 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (SAA) operations. The compare/select and vector search instructions are also provided. As shown in Figure 2 on Page 4, the Blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs, and a 40-bit shifter.
ADSP-BF538/ADSP-BF538F 0xFFFF FFFF CORE MMR REGISTERS (2M BYTES) 0xFFE0 0000 SYSTEM MMR REGISTERS (2M BYTES) 0xFFC0 0000 RESERVED 0xFFB0 1000 0xFFB0 0000 In addition, multiple L1 memory blocks are provided, offering a configurable mix of SRAM and cache. The memory management Unit (MMU) provides memory protection for individual tasks that may be operating on the core and can protect system registers from unintended access.
ADSP-BF538/ADSP-BF538F External (Off-Chip) Memory External memory is accessed via the external bus interface unit (EBIU). This 16-bit interface provides a glueless connection to a bank of synchronous DRAM (SDRAM) as well as up to four banks of asynchronous memory devices including flash, EPROM, ROM, SRAM, and memory mapped I/O devices. The PC133-compliant SDRAM controller can be programmed to interface to up to 128M bytes of SDRAM.
ADSP-BF538/ADSP-BF538F ensures that servicing of a higher priority event takes precedence over servicing of a lower priority event. The controller provides support for five different types of events: Table 2. Core Event Controller (CEC) Priority (0 is Highest) Event Class EVT Entry 0 Emulation/Test Control EMU 1 Reset RST • Reset – This event resets the processor.
ADSP-BF538/ADSP-BF538F Table 3.
ADSP-BF538/ADSP-BF538F faces, including the SDRAM controller and the asynchronous memory controller. DMA capable peripherals include the SPORTs, SPI ports, UARTs, and PPI. Each individual DMA capable peripheral has at least one dedicated DMA channel. The DMA controllers support both 1-dimensional (1-D) and 2-dimensional (2-D) DMA transfers. DMA transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks.
ADSP-BF538/ADSP-BF538F timer, or as a mechanism for measuring pulse widths and periods of external events. These timers can be synchronized to an external clock input to the PF1 pin (TACLK), an external clock input to the PPI_CLK pin (TMRCLK), or to the internal SCLK. • Interrupts – Each transmit and receive port generates an interrupt upon completing the transfer of a data word or after transferring an entire data buffer or buffers through DMA.
ADSP-BF538/ADSP-BF538F UART PORTS The ADSP-BF538/ADSP-BF538F processors incorporate three full-duplex universal asynchronous receiver/transmitter (UART) ports, which are fully compatible with PC standard UARTs. The UART ports provide a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA supported, asynchronous transfers of serial data. The UART ports include support for 5 data bits to 8 data bits, 1 stop bit or 2 stop bits, and none, even, or odd parity.
ADSP-BF538/ADSP-BF538F The PPI supports a variety of general-purpose and ITU-R 656 modes of operation. In general-purpose mode, the PPI provides half-duplex, bidirectional data transfer with up to 16 bits of data. Up to 3 frame synchronization signals are also provided. In ITU-R 656 mode, the PPI provides half-duplex, bi-directional transfer of 8- or 10-bit video data. Additionally, on-chip decode of embedded start-of-line (SOL) and start-of-field (SOF) preamble packets is supported.
ADSP-BF538/ADSP-BF538F The CAN clock is derived from the processor system clock (SCLK) through a programmable divider and therefore does not require an additional crystal. DYNAMIC POWER MANAGEMENT The ADSP-BF538/ADSP-BF538F processors provide four operating modes, each with a different performance/power profile. In addition, dynamic power management provides the control functions to dynamically alter the processor core supply voltage, further reducing power dissipation.
ADSP-BF538/ADSP-BF538F internal logic except for the RTC logic. The 3.3 V VDDEXT power domain supplies all the I/O except for the RTC crystal. There are no sequencing requirements for the various power domains. SET OF DECOUPLING CAPACITORS VDDEXT (LOW-INDUCTANCE) + Table 6.
ADSP-BF538/ADSP-BF538F If an external clock is used, it should be a TTL-compatible signal and must not be halted, changed, or operated below the specified frequency during normal operation. This signal is connected to the processor’s CLKIN pin. When an external clock is used, the XTAL pin must be left unconnected. Alternatively, because the ADSP-BF538/ADSP-BF538F processors include an on-chip oscillator circuit, an external crystal may be used.
ADSP-BF538/ADSP-BF538F BOOTING MODES The ADSP-BF538/ADSP-BF538F processors have three mechanisms (listed in Table 9) for automatically loading internal L1 instruction memory after a reset. A fourth mode is provided to execute from external memory, bypassing the boot sequence. Table 9. Booting Modes In addition, Bit 4 of the reset configuration register can be set by application code to bypass the normal boot sequence during a software reset.
ADSP-BF538/ADSP-BF538F Integrated Development Environments (IDEs) Board Support Packages for Evaluation Hardware For C/C++ software writing and editing, code generation, and debug support, Analog Devices offers two IDEs. Software support for the EZ-KIT Lite evaluation boards and EZExtender daughter cards is provided by software add-ins called Board Support Packages (BSPs). The BSPs contain the required drivers, pertinent release notes, and select example code for the given evaluation hardware.
ADSP-BF538/ADSP-BF538F ADDITIONAL INFORMATION The following publications that describe the ADSP-BF538/ ADSP-BF538F processors (and related processors) can be ordered from any Analog Devices sales office or accessed electronically on our website: • Getting Started with Blackfin Processors • ADSP-BF538/ADSP-BF538F Blackfin Processor Hardware Reference • ADSP-BF53x/ADSP-BF56x Blackfin Processor Programming Reference • ADSP-BF538 Blackfin Processor Anomaly List RELATED SIGNAL CHAINS A signal chain is a series
ADSP-BF538/ADSP-BF538F PIN DESCRIPTIONS The ADSP-BF538/ADSP-BF538F processors pin definitions are listed in Table 10. All pins are three-stated during and immediately after reset, except the memory interface, asynchronous memory control, and synchronous memory control pins. These pins are all driven high, with the exception of CLKOUT, which toggles at the system clock rate. If BR is active (whether or not RESET is asserted), the memory pins are also three-stated.
ADSP-BF538/ADSP-BF538F Table 10. Pin Descriptions (Continued) Pin Name I/O 2-Wire Interface Port Driver Type1 Function These pins are open-drain and require a pull-up resistor. See version 2.1 of the I2C specification for proper resistor values.
ADSP-BF538/ADSP-BF538F Table 10.
ADSP-BF538/ADSP-BF538F Table 10. Pin Descriptions (Continued) Pin Name I/O Function Driver Type1 PF7/PPI12/SPI0SEL7 I/O GPIO/PPI12/SPI0 Slave Select Enable 7 C PF8/PPI11 I/O GPIO/PPI11 C PF9/PPI10 I/O GPIO/PPI10 C PF10/PPI9 I/O GPIO/PPI9 C PF11/PPI8 I/O GPIO/PPI8 C PF12/PPI7 I/O GPIO/PPI7 C PF13/PPI6 I/O GPIO/PPI6 C PF14/PPI5 I/O GPIO/PPI5 C PF15/PPI4 I/O GPIO/PPI4 C RTXI I RTC Crystal Input (This pin should be pulled low when not used.
ADSP-BF538/ADSP-BF538F SPECIFICATIONS Note that component specifications are subject to change without notice. OPERATING CONDITIONS Parameter Conditions 1, 2 Min Nom Max Unit VDDINT VDDINT Internal Supply Voltage Internal Supply Voltage 533 MHz Speed Grade Models 400 MHz Speed Grade Models1, 2 0.8 0.8 1.25 1.2 1.375 1.32 V V VDDEXT External Supply Voltage Models with on-chip flash2 2.7 3.3 3.6 V 2.25 3.0 3.6 V 3.
ADSP-BF538/ADSP-BF538F The following tables describe the voltage/frequency requirements for the ADSP-BF538/ADSP-BF538F processor clocks. Take care in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock (Table 11 and Table 12) and system clock (Table 14) specifications. Table 13 describes phase-locked loop operating conditions. Table 11. Core Clock (CCLK) Requirements — 400 MHz Models Parameter fCCLK CLK Frequency (VDDINT = 1.14 V Minimum) fCCLK CLK Frequency (VDDINT = 1.
ADSP-BF538/ADSP-BF538F ELECTRICAL CHARACTERISTICS Parameter1 2 VOH High Level Output Voltage VOL Low Level Output Voltage2 IIH High Level Input Current3 High Level Input Current JTAG IIHP 4 3 Low Level Input Current IIL 5 Test Conditions Min VDDEXT = +3.0 V, IOH = –0.5 mA 2.4 Typ Max Unit VDDEXT = 3.0 V, IOL = 2.0 mA 0.4 V VDDEXT= Maximum, VIN = VDD Maximum 10.0 μA VDDEXT = Maximum, VIN = VDD Maximum 50.0 μA VDDEXT = Maximum, VIN = 0 V 10.
ADSP-BF538/ADSP-BF538F Table 15. Static Current (mA)1 VDDINT (V) TJ (°C) 0.80 V 0.85 V 0.90 V 0.95 V 1.00 V 1.05 V 1.10 V 1.15 V 1.20 V 1.25 V 1.30 V 1.32 V 1.375 V –40 6.4 7.7 8.8 10.4 12.0 14.0 16.1 18.9 21.9 25.2 28.7 30.6 35.9 –25 9.2 10.9 12.5 14.5 16.7 19.3 22.1 25.6 29.5 33.7 38.1 40.5 47.2 0 16.8 18.9 21.5 24.4 27.7 31.7 35.8 40.5 45.8 51.6 58.2 61.0 69.8 25 32.9 37.2 41.4 46.2 51.8 57.4 64.2 72.3 80.0 89.3 98.9 103.3 116.
ADSP-BF538/ADSP-BF538F ABSOLUTE MAXIMUM RATINGS PACKAGE INFORMATION Stresses greater than those listed below may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ADSP-BF538/ADSP-BF538F TIMING SPECIFICATIONS Component specifications are subject to change with PCN notice. Clock and Reset Timing Table 21 and Figure 10 describe clock and reset operations. Per Absolute Maximum Ratings on Page 27, combinations of CLKIN and clock multipliers must not select core/peripheral clocks that exceed maximum operating conditions. Table 21.
ADSP-BF538/ADSP-BF538F Asynchronous Memory Read Cycle Timing Table 23 and Table 24 on Page 30 and Figure 12 and Figure 13 on Page 30 describe asynchronous memory read cycle operations for synchronous and for asynchronous ARDY. Table 23. Asynchronous Memory Read Cycle Timing with Synchronous ARDY Parameter Min Max Unit Timing Requirements tSDAT DATA15–0 Setup Before CLKOUT 2.1 ns tHDAT DATA15–0 Hold After CLKOUT 0.8 ns tSARDY ARDY Setup Before the Falling Edge of CLKOUT 4.
ADSP-BF538/ADSP-BF538F Table 24. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY Parameter Min Max Unit Timing Requirements tSDAT DATA15–0 Setup Before CLKOUT 2.1 tHDAT DATA15–0 Hold After CLKOUT 0.8 tDANR ARDY Negated Delay from AMSx Asserted1 tHAA ARDY Asserted Hold After ARE Negated ns ns (S + RA – 2) tSCLK 0.0 ns ns Switching Characteristics tDO Output Delay After CLKOUT2 tHO Output Hold After CLKOUT2 1 2 6.0 0.
ADSP-BF538/ADSP-BF538F Asynchronous Memory Write Cycle Timing Table 25 and Table 26 on Page 32 and Figure 14 and Figure 15 on Page 32 describe asynchronous memory write cycle operations for synchronous and for asynchronous ARDY. Table 25. Asynchronous Memory Write Cycle Timing with Synchronous ARDY Parameter Min Max Unit Timing Requirements tSARDY ARDY Setup Before the Falling Edge of CLKOUT 4.0 ns tHARDY ARDY Hold After the Falling Edge of CLKOUT 0.
ADSP-BF538/ADSP-BF538F Table 26. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY Parameter Min Max Unit (S + WA – 2) × tSCLK ns Timing Requirements tDANW ARDY Negated Delay from AMSx Asserted1 tHAA ARDY Asserted Hold After ARE Negated 0.0 ns Switching Characteristics tDDAT DATA15–0 Disable After CLKOUT tENDAT DATA15–0 Enable After CLKOUT tDO Output Delay After CLKOUT2 tHO Output Hold After CLKOUT2 1 2 6.0 1.0 6.0 0.
ADSP-BF538/ADSP-BF538F SDRAM Interface Timing Table 27. SDRAM Interface Timing Parameter Min Max Unit Timing Requirements tSSDAT DATA Setup Before CLKOUT 2.1 ns tHSDAT DATA Hold After CLKOUT 0.8 ns Switching Characteristics tSCLK CLKOUT Period 7.5 ns tSCLKH CLKOUT Width High 2.5 ns tSCLKL CLKOUT Width Low 2.5 ns tDCAD Command, ADDR, Data Delay After CLKOUT tHCAD Command, ADDR, Data Hold After CLKOUT1 tDSDAT Data Disable After CLKOUT tENSDAT Data Enable After CLKOUT 1 1 6.
ADSP-BF538/ADSP-BF538F External Port Bus Request and Grant Cycle Timing Table 28 and Table 29 on Page 35 and Figure 17 and Figure 18 on Page 35 describe external port bus request and grant cycle operations for synchronous and for asynchronous BR. Table 28. External Port Bus Request and Grant Cycle Timing with Synchronous BR Parameter Min Max Unit Timing Requirements tBS BR Setup to Falling Edge of CLKOUT 4.6 ns tBH Falling Edge of CLKOUT to BR Deasserted Hold Time 1.
ADSP-BF538/ADSP-BF538F Table 29. External Port Bus Request and Grant Cycle Timing with Asynchronous BR Parameter Min Max Unit Timing Requirement tWBR BR Pulse Width 2 × tSCLK ns Switching Characteristics tSD CLKOUT Low to AMSx, Address, and ARE/AWE Disable tSE CLKOUT Low to AMSx, Address, and ARE/AWE Enable 4.5 ns tDBG CLKOUT High to BG High Setup 3.6 ns tEBG CLKOUT High to BG Deasserted Hold Time 3.6 ns tDBH CLKOUT High to BGH High Setup 3.
ADSP-BF538/ADSP-BF538F Parallel Peripheral Interface Timing Table 30 and Figure 19, Figure 20, Figure 21, and Figure 22 describe parallel peripheral interface operations. Table 30. Parallel Peripheral Interface Timing Parameter Min Max Unit Timing Requirements tPCLKW PPI_CLK Width 6.0 1 ns tPCLK PPI_CLK Period tSFSPE External Frame Sync Setup Before PPI_CLK tHFSPE External Frame Sync Hold After PPI_CLK 1.0 ns tSDRPE Receive Data Setup Before PPI_CLK 2.
ADSP-BF538/ADSP-BF538F DATA DRIVEN / FRAME SYNC SAMPLED PPI_CLK tSFSPE tHFSPE tPCLKW tPCLK PPI_FS1/2 tDDTPE tHDTPE PPI_DATA Figure 21. PPI GP Tx Mode with External Frame Sync Timing FRAME SYNC DRIVEN DATA DRIVEN tPCLK PPI_CLK tHOFSPE tDFSPE tPCLKW PPI_FS1/2 tDDTPE tHDTPE PPI_DATA Figure 22. PPI GP Tx Mode with Internal Frame Sync Timing Rev.
ADSP-BF538/ADSP-BF538F Serial Port Timing Table 31 through Table 34 on Page 41 and Figure 23 on Page 39 through Figure 26 on Page 41 describe serial port operations. Table 31. Serial Ports—External Clock Parameter Min Max Unit Timing Requirements tSFSE TFSx/RFSx Setup Before TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)1 tHFSE TFSx/RFSx Hold After TSCLKx/RSCLKx (Externally Generated TFSx/RFSx) tSDRE Receive Data Setup Before RSCLKx1 1 1 3.0 ns 3.0 ns 3.0 ns 3.0 ns 4.
ADSP-BF538/ADSP-BF538F DATA RECEIVE—INTERNAL CLOCK DATA RECEIVE—EXTERNAL CLOCK DRIVE EDGE DRIVE EDGE SAMPLE EDGE SAMPLE EDGE tSCLKE tSCLKEW tSCLKIW RSCLKx RSCLKx tDFSE tDFSI tHOFSI tHOFSE RFSx (OUTPUT) RFSx (OUTPUT) tSFSI tHFSI RFSx (INPUT) tSFSE tHFSE tSDRE tHDRE RFSx (INPUT) tSDRI tHDRI DRx DRx DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE DATA TRANSMIT—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE tSCLKIW SAMPLE EDGE t SCLKEW TSCLKx tSCLKE TSCLKx tD FSI tDFSE tHOFSI tHOFSE TFSx (
ADSP-BF538/ADSP-BF538F Table 33. Serial Ports—Enable and Three-State Parameter Min Max Unit Switching Characteristics tDTENE Data Enable Delay from External TSCLKx1 tDDTTE Data Disable Delay from External TSCLKx tDTENI Data Enable Delay from Internal TSCLKx1 tDDTTI Data Disable Delay from Internal TSCLKx 0 1, 2, 3 10 –2 1, 2, 3 Referenced to drive edge. 2 Applicable to multichannel mode only. 3 TSCLKx is tied to RSCLKx. DRIVE EDGE DRIVE EDGE TSCLKx tDTENE/I tDDTTE/I DTx Figure 25.
ADSP-BF538/ADSP-BF538F Table 34. External Late Frame Sync Parameter Min Max Unit 10.0 ns Switching Characteristics tDDTLFSE tDTENLFS Data Delay from Late External TFSx or External RFSx in multichannel mode, MFD = 01, 2 Data Enable from Late FS or multichannel mode, MFD = 0 1, 2 1 In multichannel mode, TFSx enable and TFSx valid follow tDTENLFS and tDDTLFSE. 2 If external RFSx/TFSx setup to RSCLKx/TSCLKx > tSCLKE/2, then tDDTTE/I and tDTENE/I apply; otherwise tDDTLFSE and tDTENLFS apply.
ADSP-BF538/ADSP-BF538F Serial Peripheral Interface Ports—Master Timing Table 35 and Figure 27 describe SPI ports master operations. Table 35. Serial Peripheral Interface (SPI) Ports—Master Timing Parameter Min Max Unit Timing Requirements tSSPIDM Data Input Valid to SCKx Edge (Data Input Setup) 9.0 ns tHSPIDM SCKx Sampling Edge to Data Input Invalid –1.5 ns Switching Characteristics tSDSCIM SPIxSELy Low to First SCKx edge 2 × tSCLK –1.5 ns tSPICHM Serial Clock High Period 2 × tSCLK –1.
ADSP-BF538/ADSP-BF538F Serial Peripheral Interface Ports—Slave Timing Table 36 and Figure 28 describe SPI ports slave operations. Table 36. Serial Peripheral Interface (SPI) Ports—Slave Timing Parameter Min Max Unit Timing Requirements tSPICHS Serial Clock High Period 2 × tSCLK –1.5 tSPICLS Serial Clock Low Period 2 × tSCLK –1.5 ns tSPICLK Serial Clock Period 4 × tSCLK ns tHDS Last SCKx Edge to SPIxSS Not Asserted 2 × tSCLK –1.5 ns tSPITDS Sequential Transfer Delay 2 × tSCLK –1.
ADSP-BF538/ADSP-BF538F General-Purpose Port Timing Table 37 and Figure 29 describe general-purpose operations. Table 37. General-Purpose Port Timing Parameter Min Max Unit Timing Requirement tWFI GP Port Pin Input Pulse Width tSCLK + 1 ns Switching Characteristic tGPOD GP Port Pin Output Delay from CLKOUT Low 6 ns CLKOUT tGPOD GPIO OUTPUT tWFI GPIO INPUT Figure 29. General-Purpose Port Cycle Timing Timer Clock Timing Table 38 and Figure 30 describe timer clock timing. Table 38.
ADSP-BF538/ADSP-BF538F Timer Cycle Timing Table 39 and Figure 31 describe timer expired operations. The input signal is asynchronous in “width capture mode” and “external clock mode” and has an absolute maximum input frequency of (fSCLK/2) MHz. Table 39.
ADSP-BF538/ADSP-BF538F Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing For information on the UART port receive and transmit operations, see the ADSP-BF538 Blackfin Processor Hardware Reference. JTAG Test and Emulation Port Timing Table 40 and Figure 32 describe JTAG port operations. Table 40.
ADSP-BF538/ADSP-BF538F OUTPUT DRIVE CURRENTS 150 Figure 33 through Figure 40 on Page 48 show typical currentvoltage characteristics for the output drivers of the ADSPBF538/ADSP-BF538F processors. The curves represent the current drive capability of the output drivers as a function of output voltage. 100 SOURCE CURRENT (mA) VDDEXT = 2.75V 120 100 SOURCE CURRENT (mA) 80 VDDEXT = 2.75V 50 VOH 0 -50 VOL -100 60 VOH 40 -150 20 0 0.5 1.0 0 1.5 2.0 2.5 3.
ADSP-BF538/ADSP-BF538F 80 100 80 60 VDDEXT = 2.75V 60 40 SOURCE CURRENT (mA) SOURCE CURRENT (mA) VDDEXT = 2.75V VOH 20 0 -20 VOL 40 VOH 20 0 -20 -40 VOL -40 -60 -60 -80 0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.5 1.0 SOURCE VOLTAGE (V) Figure 37. Drive Current C (Low VDDEXT) 2.0 2.5 3.0 Figure 39. Drive Current D (Low VDDEXT) 150 100 80 VDDEXT = 3.0 V VDDEXT = 3.3 V 60 VDDEXT = 3.6 V VDDEXT = 3.0 V VDDEXT = 3.3 V VDDEXT = 3.6 V 100 SOURCE CURRENT (mA) SOURCE CURRENT (mA) 1.
ADSP-BF538/ADSP-BF538F Output Enable Time Measurement 0 Output pins are considered to be enabled when they have made a transition from a high impedance state to the point when they start driving. -10 SOURCE CURRENT (mA) VDDEXT = 2.75V The output enable time tENA is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output starts driving as shown on the right side of Figure 44, “Output Enable/Disable,” on page 49. -20 -30 VOL -40 -50 -60 0 0.
ADSP-BF538/ADSP-BF538F Example System Hold Time Calculation Capacitive Loading 14 RISE AND FALL TIME ns (10% to 90%) To determine the data output hold time in a particular system, first calculate tDECAY using the equation given above. Choose V to be the difference between the ADSP-BF538/ADSP-BF538F processor’s output voltage and the input threshold for the device requiring the hold time. CL is the total bus capacitance (per data line), and IL is the total leakage or three-state current (per data line).
ADSP-BF538/ADSP-BF538F 30 RISE AND FALL TIME ns (10% to 90%) RISE AND FALL TIME ns (10% to 90%) 12 10 RISE TIME 8 FALL TIME 6 4 0 50 100 150 LOAD CAPACITANCE (pF) 200 FALL TIME 10 50 100 150 LOAD CAPACITANCE (pF) 200 250 Figure 50. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for Driver C at VDDEXT = 2.7 V (Min) 20 RISE AND FALL TIME ns (10% to 90%) 10 RISE AND FALL TIME ns (10% to 90%) 15 0 0 250 Figure 48. Typical Rise and Fall Times (10% to 90%) vs.
ADSP-BF538/ADSP-BF538F 132 16 14 128 RISE TIME 12 FALL TIME ns (10% to 90%) RISE AND FALL TIME ns (10% to 90%) 18 10 FALL TIME 8 6 4 2 0 124 FALL TIME 120 116 112 0 50 100 150 LOAD CAPACITANCE (pF) 200 250 108 0 Figure 52. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for Driver D at VDDEXT = 2.7 V (Min) 50 100 150 LOAD CAPACITANCE (pF) 200 250 Figure 54. Typical Fall Time (10% to 90%) vs. Load Capacitance for Driver E at VDDEXT = 2.
ADSP-BF538/ADSP-BF538F THERMAL CHARACTERISTICS Table 41. Thermal Characteristics BC-316-2 without Flash To determine the junction temperature on the application printed circuit board use Parameter Condition Typical Unit T J = T CASE + JT P D JA 0 Linear m/s Airflow 25.4 ⴗC/W JMA 1 Linear m/s Airflow 22.8 ⴗC/W JMA 2 Linear m/s Airflow JC where: TJ = junction temperature (ⴗC) TCASE = case temperature (ⴗC) measured by customer at top center of package.
ADSP-BF538/ADSP-BF538F 316-BALL CSP_BGA BALL ASSIGNMENT Table 43 on Page 55 lists the CSP_BGA ball assignment by ball number. Table 44 on Page 56 lists the CSP_BGA ball assignment by signal.
ADSP-BF538/ADSP-BF538F Table 43. 316-Ball CSP_BGA Ball Assignment (Numerically by Ball Number) Ball No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C1 C2 C3 C4 C5 C6 Signal GND PF10 PF11 PPI_CLK PPI0 PPI2 PF15 PF13 VDDRTC RTXO RTXI GND CLKIN XTAL GND NC GND GPW VROUT1 GND PF8 GND PF9 PF3 PPI1 PPI3 PF14 PF12 SCL0 SDA0 CANRX CANTX NMI RESET VDDEXT GND PC9 GND GND VROUT0 PF6 PF7 GND GND RX1 TX1 Ball No.
ADSP-BF538/ADSP-BF538F Table 44. 316-Ball CSP_BGA Ball Assignment (Alphabetically by Signal) Signal ABE0 ABE1 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 AMS0 AMS1 AMS2 AMS3 AOE ARDY ARE AWE BG BGH BMODE0 BMODE1 BR CANRX CANTX CLKIN CLKOUT DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 Ball No.
ADSP-BF538/ADSP-BF538F OUTLINE DIMENSIONS Dimensions in the outline dimensions figures are shown in millimeters. A1 BALL CORNER 17.10 17.00 SQ 16.90 A B C D E F G H J K L M N P R T U V W Y 15.20 BSC SQ 0.80 BSC TOP VIEW 1.45 1.36 1.27 A1 BALL CORNER 20 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 7 5 3 1 BOTTOM VIEW DETAIL A DETAIL A 1.08 1.01 0.94 0.35 NOM 0.30 MIN 0.50 COPLANARITY 0.20 0.45 0.40 BALL DIAMETER SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-275-MMAB-1.
ADSP-BF538/ADSP-BF538F ORDERING GUIDE Model 1 Temperature Range2 ADSP-BF538BBCZ-4A –40C to +85C 400 MHz N/A 1.2 V internal, 2.5 V or 3.3 V I/O 316-Ball CSP_BGA BC-316-2 ADSP-BF538BBCZ-5A –40C to +85C 533 MHz N/A 1.25 V internal, 2.5 V or 3.3 V I/O 316-Ball CSP_BGA BC-316-2 ADSP-BF538BBCZ-4F8 –40C to +85C 400 MHz 8M bit 1.2 V internal, 3.0 V or 3.3 V I/O 316-Ball CSP_BGA BC-316-2 ADSP-BF538BBCZ-5F8 –40C to +85C 533 MHz 8M bit 1.25 V internal, 3.0 V or 3.
ADSP-BF538/ADSP-BF538F Rev.
ADSP-BF538/ADSP-BF538F ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06700-0-11/13(E) Rev.