Blackfin Embedded Symmetric Multiprocessor ADSP-BF561 FEATURES Dual symmetric 600 MHz high performance Blackfin cores 328K bytes of on-chip memory (see Memory Architecture on Page 4) Each Blackfin core includes Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register and instruction model for ease of pro gramming and compiler-friendly support Advanced debug, trace, and performance monitoring Wide range of operating voltages, (see Operating Conditions on Page 20) 256-ball C
ADSP-BF561 TABLE OF CONTENTS Features ................................................................. 1 Designing an Emulator-Compatible Processor Board ... 16 Peripherals ............................................................. 1 Related Documents .............................................. 16 Table of Contents ..................................................... 2 Pin Descriptions .................................................... 17 Revision History ....................................
ADSP-BF561 GENERAL DESCRIPTION The ADSP-BF561 processor is a high performance member of the Blackfin® family of products targeting a variety of multime dia, industrial, and telecommunications applications. At the heart of this device are two independent Analog Devices Blackfin processors.
ADSP-BF561 ADDRESS ARITHMETIC UNIT L3 B3 M3 I2 L2 B2 M2 I1 L1 B1 M1 I0 L0 B0 M0 SP FP P5 DAG1 P4 P3 DAG0 P2 32 32 P1 P0 TO MEMORY DA1 DA0 I3 32 PREG 32 RAB SD LD1 LD0 32 32 32 ASTAT 32 32 SEQUENCER R7.H R6.H R7.L R6.L R5.H R5.L R4.H R4.L R3.H R3.L R2.H R2.L R1.H R1.L R0.H R0.L 16 ALIGN 16 8 8 8 8 DECODE BARREL SHIFTER 40 40 A0 32 40 40 A1 LOOP BUFFER CONTROL UNIT 32 DATA ARITHMETIC UNIT Figure 2.
ADSP-BF561 CORE A MEMORY MAP CORE B MEMORY MAP 0xFFFF FFFF 0xFFE0 0000 CORE MMR REGISTERS 0xFFC0 0000 0xFFB0 1000 0xFFB0 0000 0xFFA1 4000 0xFFA1 0000 0xFFA0 4000 0xFFA0 0000 0xFF90 8000 0xFF90 4000 0xFF90 0000 0xFF80 8000 0xFF80 4000 0xFF80 0000 CORE MMR REGISTERS SYSTEM MMR REGISTERS RESERVED L1 SCRATCHPAD SRAM (4K) RESERVED L1 INSTRUCTION SRAM/CACHE (16K) RESERVED L1 INSTRUCTION SRAM (16K) RESERVED RESERVED L1 DATA BANK B SRAM/CACHE (16K) L1 DATA BANK B SRAM (16K) RESERVED L1 DATA BANK A SRAM/CACH
ADSP-BF561 flexible configuration and upgradability of system memory while allowing the core to view all SDRAM as a single, contigu ous, physical address space. • Interrupts – Events that occur asynchronously to program flow. They are caused by timers, peripherals, input pins, and an explicit software instruction. The asynchronous memory controller can also be programmed to control up to four banks of devices with very flexible timing parameters for a wide variety of devices.
ADSP-BF561 writing the appropriate values into the Interrupt Assignment Registers (SIC_IAR7–0). Table 2 describes the inputs into the SIC and the default mappings into the CEC. Table 2.
ADSP-BF561 even though the event may be latched in the ILAT register. This register may be read from or written to while in supervisor mode. Note that general-purpose interrupts can be globally enabled and disabled with the STI and CLI instructions, respectively. • CEC Interrupt Pending Register (IPEND) – The IPEND register keeps track of all nested events. A set bit in the IPEND register indicates the event is currently active or nested at some level.
ADSP-BF561 After a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the timer control register, which is set only upon a watchdog gener ated reset. • DMA operations with single-cycle overhead – Each SPORT can automatically receive and transmit multiple buffers of memory data. The DSP can link or chain sequences of DMA transfers between a SPORT and memory. The timer is clocked by the system clock (SCLK) at a maximum frequency of fSCLK.
ADSP-BF561 • PIO (programmed I/O) – The processor sends or receives data by writing or reading I/O-mapped UART registers. The data is double-buffered on both transmit and receive. • DMA (direct memory access) – The DMA controller trans fers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated DMA channels, one for transmit and one for receive.
ADSP-BF561 Frame Capture Mode Table 3. Power Settings Frame capture mode allows the video source(s) to act as a slave (e.g., for frame capture). The ADSP-BF561 processors control when to read from the video source(s). PPI_FS1 is an HSYNC output and PPI_FS2 is a VSYNC output. Output Mode Output mode is used for transmitting video or other data with up to three output frame syncs.
ADSP-BF561 regulator for the processor can be shut off by writing b#00 to the FREQ bits of the VR_CTL register. This disables both CCLK and SCLK. Furthermore, it sets the internal power supply volt age (VDDINT) to 0 V to provide the lowest static power dissipation. Any critical information stored internally (memory contents, register contents, etc.) must be written to a nonvolatile storage device prior to removing power if the processor state is to be preserved.
ADSP-BF561 board. All internal and I/O power supplies should be well bypassed with bypass capacitors placed as close to the ADSP-BF561 processors as possible. Blackfin CLKOUT TO PLL CIRCUITRY For further details on the on-chip voltage regulator and related board design guidelines, see the Switching Regulator Design Considerations for ADSP-BF533 Blackfin Processors (EE-228) applications note on the Analog Devices web site (www.ana log.com)—use site search on “EE-228”.
ADSP-BF561 The core clock (CCLK) frequency can also be dynamically changed by means of the CSEL1–0 bits of the PLL_DIV register. Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in Table 6. This programmable core clock capability is useful for fast core frequency modifications. Table 6.
ADSP-BF561 • All registers, I/O, and memory are mapped into a unified 4G byte memory space providing a simplified program ming model. • Set conditional breakpoints on registers, memory, and stacks. • Microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and extraction; integer operations on 8-, 16-, and 32-bit data types; and separate user and ker nel stack pointers. • Perform linear or statistical profiling of program execution.
ADSP-BF561 In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the Blackfin processor family. Third party software tools include DSP libraries, real-time operating systems, and block diagram design tools.
ADSP-BF561 PIN DESCRIPTIONS ADSP-BF561 pin definitions are listed in Table 8. In order to maintain maximum function and reduce package size and pin count, some pins have multiple functions. In cases where pin function is reconfigurable, the default state is shown in plain text, while alternate functionality is shown in italics. All pins are three-stated during and immediately after reset, except the external memory interface, asynchronous memory control, and synchronous memory control pins.
ADSP-BF561 Table 8.
ADSP-BF561 Table 8.
ADSP-BF561 SPECIFICATIONS Component specifications are subject to change without notice.
ADSP-BF561 Table 11. Phase-Locked Loop Operating Conditions Parameter Voltage Controlled Oscillator (VCO) Frequency Min 50 Max Maximum fCCLK Unit MHz Table 12. System Clock (SCLK) Requirements Parameter1 fSCLK fSCLK 1 2 Max VDDEXT = 2.5V/3.3V 1332 100 CLKOUT/SCLK Frequency (VDDINT ≥ 1.14 V) CLKOUT/SCLK Frequency (VDDINT < 1.14 V) Unit MHz MHz tSCLK (= 1/fSCLK) must be greater than or equal to tCCLK. Rounded number. Guaranteed to tSCLK = 7.5 ns. See Table 20 on Page 26.
ADSP-BF561 ABSOLUTE MAXIMUM RATINGS PACKAGE INFORMATION Stresses greater than those listed in Table 13 may cause perma nent damage to the device. These are stress ratings only. Functional operation of the device at these or any other condi tions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ADSP-BF561 TIMING SPECIFICATIONS Clock and Reset Timing Table 16 and Figure 8 describe clock and reset operations. Per Absolute Maximum Ratings on Page 22, combinations of CLKIN and clock multipliers must not result in core/system clocks exceeding the maximum limits allowed for the processor, including system clock restrictions related to supply voltage. Table 16.
ADSP-BF561 Asynchronous Memory Read Cycle Timing Table 18. Asynchronous Memory Read Cycle Timing Parameter Timing Requirements tSDAT DATA31 –0 Setup Before CLKOUT tHDAT DATA31–0 Hold After CLKOUT tSARDY ARDY Setup Before CLKOUT tHARDY ARDY Hold After CLKOUT Switching Characteristics tDO Output Delay After CLKOUT1 tHO Output Hold After CLKOUT 1 1 Min Max Unit ns ns ns ns 2.1 0.8 4.0 0.0 ns ns 6.0 0.8 Output pins include AMS3–0, ABE3–0, ADDR25–2, AOE, ARE.
ADSP-BF561 Asynchronous Memory Write Cycle Timing Table 19. Asynchronous Memory Write Cycle Timing Parameter Timing Requirements tSARDY ARDY Setup Before CLKOUT tHARDY ARDY Hold After CLKOUT Switching Characteristics tDDAT DATA31–0 Disable After CLKOUT DATA31–0 Enable After CLKOUT tENDAT tDO Output Delay After CLKOUT1 tHO Output Hold After CLKOUT 1 1 Min 4.0 0.0 6.0 6.0 0.
ADSP-BF561 SDRAM Interface Timing Table 20. SDRAM Interface Timing Parameter Timing Requirements tSSDAT DATA Setup Before CLKOUT tHSDAT DATA Hold After CLKOUT Switching Characteristics tDCAD Command, ADDR, Data Delay After CLKOUT1 Command, ADDR, Data Hold After CLKOUT1 tHCAD tDSDAT Data Disable After CLKOUT tENSDAT Data Enable After CLKOUT tSCLK CLKOUT Period tSCLKH CLKOUT Width High tSCLKL CLKOUT Width Low 1 Min 4.0 0.8 4.0 1.0 7.5 2.5 2.
ADSP-BF561 External Port Bus Request and Grant Cycle Timing Table 21 and Figure 13 describe external port bus request and bus grant operations. Table 21.
ADSP-BF561 Parallel Peripheral Interface Timing Table 22, and Figure 14 through Figure 17 on Page 30, describe default Parallel Peripheral Interface operations. If bit 4 of the PLL_CTL register is set, then Figure 18 on Page 30 and Figure 19 on Page 31 apply. Table 22.
ADSP-BF561 DATA0 IS SAMPLED FRAME SYNC IS SAMPLED FOR DATA0 DATA1 IS SAMPLED PPIxCLK POLC = 0 PPIxCLK POLC = 1 t HFSPE tSFSPE POLS = 1 PPIxSYNC1 POLS = 0 POLS = 1 PPIxSYNC2 POLS = 0 t SDRPE t HDRPE PPIx_DATA Figure 15. PPI GP Rx Mode with External Frame Sync Timing (Default) FRAME SYNC IS DRIVEN OUT DATA0 IS DRIVEN OUT PPIxCLK POLC = 0 PPIxCLK POLC = 1 t DFSPE tHOFSPE POLS = 1 PPIxSYNC1 POLS = 0 POLS = 1 PPIxSYNC2 POLS = 0 tDDTPE tHDTPE PPIx_DATA DATA0 Figure 16.
ADSP-BF561 FRAME SYNC IS SAMPLED DATA0 IS DRIVEN OUT PPIxCLK POLC = 0 PPIxCLK POLC = 1 tHFSPE t SFSPE POLS = 1 PPxSYNC1 POLS = 0 POLS = 1 PPIxSYNC2 POLS = 0 t HDTPE PPIx_DATA DATA0 tDDTPE Figure 17. PPI GP Tx Mode with External Frame Sync Timing (Default) DATA SAMPLING/ FRAME SYNC SAMPLING EDGE DATA SAMPLING/ FRAME SYNC SAMPLING EDGE PPIxCLK POLC = 0 PPIxCLK POLC = 1 tSFSPE t HFSPE POLS = 1 PPIxSYNC1 POLS = 0 POLS = 1 PPIxSYNC2 POLS = 0 tSDRPE tHDRPE PPIx_DATA Figure 18.
ADSP-BF561 DATA DRIVING/ FRAME SYNC SAMPLING EDGE DATA DRIVING/ FRAME SYNC SAMPLING EDGE PPIxCLK POLC = 0 PPIxCLK POLC = 1 t HFSPE t SFSPE POLS = 1 PPIxSYNC1 POLS = 0 POLS = 1 PPIxSYNC2 POLS = 0 tDDTPE t HDTPE PPIx_DATA Figure 19. PPI GP Tx Mode with External Frame Sync Timing (Bit 4 of PLL_CTL Set) Rev.
ADSP-BF561 Serial Ports Table 23 through Table 26 on Page 34 and Figure 20 on Page 33 through Figure 22 on Page 34 describe Serial Port operations. Table 23.
ADSP-BF561 DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE tSCLKIW DATA RECEIVE—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE SAMPLE EDGE tSCLKW RSCLKx RSCLKx tDFSIR tDFSE tHOFSIR tSFSI tHFSI tHOFSE tSFSE tHFSE tSDRE tHDRE RFSx RFSx tSDRI tHDRI DRx DRx NOTES 1. EITHER THE RISING EDGE OR THE FALLING EDGE OF SCLK (EXTERNAL OR INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
ADSP-BF561 Table 25. Serial Ports—Enable and Three-State Parameter Switching Characteristics Data Enable Delay from External TSCLKx1 tDTENE tDDTTE Data Disable Delay from External TSCLKx1 tDTENI Data Enable Delay from Internal TSCLKx1 tDDTTI Data Disable Delay from Internal TSCLKx1 1 Min Max 0 10.0 –2.0 3.0 Unit ns ns ns ns Referenced to drive edge. Table 26.
ADSP-BF561 Serial Peripheral Interface (SPI) Port— Master Timing Table 27 and Figure 23 describe SPI port master operations. Table 27.
ADSP-BF561 Serial Peripheral Interface (SPI) Port— Slave Timing Table 28 and Figure 24 describe SPI port slave operations. Table 28.
ADSP-BF561 Universal Asynchronous Receiver Transmitter (UART) Port—Receive and Transmit Timing Figure 25 describes UART port receive and transmit operations. The maximum baud rate is SCLK/16. As shown in Figure 25, there is some latency between the generation internal UART interrupts and the external data operations. These latencies are negligible at the data transmission rates for the UART.
ADSP-BF561 Programmable Flags Cycle Timing Table 29 and Figure 26 describe programmable flag operations. Table 29. Programmable Flags Cycle Timing Parameter Timing Requirement tWFI Flag Input Pulse Width Switching Characteristic tDFO Flag Output Delay from CLKOUT Low Min Max tSCLK + 1 ns 6 CLKOUT tDFO PFx (OUTPUT) FLAG OUTPUT tWFI PFx (INPUT) FLAG INPUT Figure 26. Programmable Flags Cycle Timing Rev.
ADSP-BF561 Timer Cycle Timing Table 30 and Figure 27 describe timer expired operations. The input signal is asynchronous in width capture mode and exter nal clock mode and has an absolute maximum input frequency of fSCLK/2 MHz. Table 30.
ADSP-BF561 JTAG Test and Emulation Port Timing Table 31 and Figure 28 describe JTAG port operations. Table 31.
ADSP-BF561 OUTPUT DRIVE CURRENTS 150 150 VDDEXT = 2.75V VDDEXT = 2.50V VDDEXT = 2.25V SOURCE CURRENT (mA) 100 VDDEXT = 2.75V VDDEXT = 2.50V VDDEXT = 2.25V 100 SOURCE CURRENT (mA) Figure 29 through Figure 36 on Page 42 show typical current voltage characteristics for the output drivers of the ADSP-BF561 processor. The curves represent the current drive capability of the output drivers as a function of output voltage. Refer to Table 8 on Page 17 to identify the driver type for a pin.
ADSP-BF561 POWER DISSIPATION 100 60 SOURCE CURRENT (mA) Many operating conditions can affect power dissipation. System designers should refer to Estimating Power for ADSP-BF561 Blackfin Processors (EE-293) on the Analog Devices website (www.analog.com)—use site search on “EE-293.” This docu ment provides detailed information for optimizing your design for lowest power. VDDEXT = 3.65V VDDEXT = 3.30V VDDEXT = 2.
ADSP-BF561 t DECAY = (C L ΔV) ⁄ I L The time tDECAY is calculated with test loads CL and IL, and with ΔV equal to 0.5 V for VDDEXT (nominal) = 2.5 V/3.3 V. The time tDIS_MEASURED is the interval from when the reference sig nal switches, to when the output voltage decays ΔV from the measured output high or output low voltage. 14 RISE AND FALL TIME ns (10% to 90%) The time for the voltage on the bus to decay by ΔV is dependent on the capacitive load CL and the load current IL.
ADSP-BF561 DDEXT 18 RISE AND FALL TIME ns (10% to 90%) RISE AND FALL TIME ns (10% to 90%) 10 9 8 RISE TIME 7 6 FALL TIME 5 4 3 2 0 50 100 150 LOAD CAPACITANCE (pF) 200 10 FALL TIME 8 6 4 50 100 150 LOAD CAPACITANCE (pF) 200 RISE AND FALL TIME ns (10% to 90%) RISE TIME 20 15 FALL TIME 10 5 12 RISE TIME 10 8 FALL TIME 6 4 2 50 100 150 LOAD CAPACITANCE (pF) 200 250 Figure 44.
ADSP-BF561 In Table 32 through Table 34, airflow measurements comply with JEDEC standards JESD51–2 and JESD51–6, and the junc tion-to-board measurement complies with JESD51–8. The junction-to-case measurement complies with MIL-STD-883 (Method 1012.1). All measurements use a 2S2P JEDEC test board. Thermal resistance θJA in Table 32 through Table 34 is the figure of merit relating to performance of the package and board in a convective environment.
ADSP-BF561 256-BALL CSP_BGA (17 mm) BALL ASSIGNMENT Table 35 lists the 256-Ball CSP_BGA (17 mm × 17 mm) ball assignment by ball number. Table 36 on Page 48 lists the ball assignment alphabetically by signal. Table 35. 256-Ball CSP_BGA (17 mm × 17 mm) Ball Assignment (Numerically by Ball Number) Ball No.
ADSP-BF561 Table 35. 256-Ball CSP_BGA (17 mm × 17 mm) Ball Assignment (Numerically by Ball Number) (Continued) Ball No. N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 Signal GND BMODE1 BMODE0 RX DR1SEC DT1SEC RFS0 DATA30 PPI1D13 PPI1D8 PPI1D6 PPI1D0 Ball No. P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 Signal PF01 PF06 PF08 PF15 NMI1 TMS NMI0 SCK RFS1 TFS1 DR0SEC DT0SEC Ball No. R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 Rev.
ADSP-BF561 Table 36. 256-Ball CSP_BGA (17 mm × 17 mm) Ball Assignment (Alphabetically by Signal) Signal ABE0 ABE1 ABE2 ABE3 ADDR02 ADDR03 ADDR04 ADDR05 ADDR06 ADDR07 ADDR08 ADDR09 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21 ADDR22 ADDR23 ADDR24 ADDR25 AMS0 AMS1 AMS2 AMS3 AOE ARDY ARE AWE BG BGH BMODE0 BMODE1 Ball No.
ADSP-BF561 Table 36. 256-Ball CSP_BGA (17 mm × 17 mm) Ball Assignment (Alphabetically by Signal) (Continued) Signal SMS1 SMS2 SMS3 SRAS SWE TCK TDI TDO TFS0 TFS1 TMS TRST Ball No. B9 A9 C9 D9 C10 R9 T10 T9 R16 P14 P10 R10 Signal TSCLK0 TSCLK1 TX VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT Ball No. M15 R14 T13 A1 A16 F5 F6 F7 F10 F11 F12 G2 Signal VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT Rev. E | Ball No.
ADSP-BF561 Figure 48 lists the top view of the 256-Ball CSP_BGA (17 mm × 17 mm) ball configuration. Figure 49 lists the bottom view. A1 BALL PAD CORNER A KEY: B C D VDDINT GND NC VDDEXT I/O VROUT E F G H J K L M N P R T 1 2 3 4 5 6 7 8 TOP VIEW 9 10 11 12 13 14 15 16 Figure 48.
ADSP-BF561 256-BALL CSP_BGA (12 mm) BALL ASSIGNMENT Table 37 lists the 256-Ball CSP_BGA (12 mm × 12 mm) ball assignment by ball number. Table 38 on Page 53 lists the ball assignment alphabetically by signal. Table 37. 256-Ball CSP_BGA (12 mm × 12 mm) Ball Assignment (Numerically by Ball Number) Ball No.
ADSP-BF561 Table 37. 256-Ball CSP_BGA (12 mm × 12 mm) Ball Assignment (Numerically by Ball Number) (Continued) Ball No. N09 N10 N11 N12 N13 N14 N15 N16 P01 P02 P03 P04 Signal TDO BMODE1 MOSI GND RFS1 GND DT0SEC TSCLK0 PPI1D8 GND PPI1D5 PF0 Ball No. P05 P06 P07 P08 P09 P10 P11 P12 P13 P14 P15 P16 Signal GND PF5 PF11 PF15 GND TRST NMI0 GND RSCLK1 TFS1 RSCLK0 DR0SEC Ball No. R01 R02 R03 R04 R05 R06 R07 R08 R09 R10 R11 R12 Rev.
ADSP-BF561 Table 38. 256-Ball CSP_BGA (12 mm × 12 mm) Ball Assignment (Alphabetically by Signal) Signal ABE0 ABE1 ABE2 ABE3 ADDR02 ADDR03 ADDR04 ADDR05 ADDR06 ADDR07 ADDR08 ADDR09 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21 ADDR22 ADDR23 ADDR24 ADDR25 AMS0 AMS1 AMS2 AMS3 AOE ARDY ARE AWE BG BGH BMODE0 BMODE1 Ball No.
ADSP-BF561 Table 38. 256-Ball CSP_BGA (12 mm × 12 mm) Ball Assignment (Alphabetically by Signal) (Continued) Signal PPI0D12 PPI0D13 PPI0D14 PPI0D15 PPI0SYNC1 PPI0SYNC2 PPI0SYNC3 PPI1CLK PPI1D0 PPI1D1 PPI1D2 PPI1D3 PPI1D4 PPI1D5 PPI1D6 PPI1D7 PPI1D8 PPI1D9 PPI1D10 PPI1D11 PPI1D12 PPI1D13 PPI1D14 PPI1D15 Ball No.
ADSP-BF561 Figure 50 lists the top view of the 256-Ball CSP_BGA (12 mm × 12 mm) ball configuration. Figure 51 lists the bottom view. A1 BALL PAD CORNER A KEY: B C D VDDINT GND NC VDDEXT I/O VROUT E F G H J K L M N P R T 1 2 3 4 5 6 7 8 TOP VIEW 9 10 11 12 13 14 15 16 Figure 50.
ADSP-BF561 297-BALL PBGA BALL ASSIGNMENT Table 39 lists the 297-Ball PBGA ball assignment numerically by ball number. Table 40 on Page 58 lists the ball assignment alphabetically by signal. Table 39. 297-Ball PBGA Ball Assignment (Numerically by Ball Number) Ball No.
ADSP-BF561 Table 39. 297-Ball PBGA Ball Assignment (Numerically by Ball Number) (Continued) Ball No. P15 P16 P17 P18 P25 P26 R01 R02 R10 R11 R12 R13 R14 R15 R16 R17 R18 R25 R26 T01 T02 T10 T11 T12 T13 T14 T15 T16 T17 T18 T25 T26 U01 U02 U10 Signal GND GND GND VDDINT DATA18 DATA21 PPI0D5 PPI0D6 VDDEXT GND GND GND GND GND GND GND VDDINT DATA20 DATA23 PPI0D3 PPI0D4 VDDEXT GND GND GND GND GND GND GND VDDINT DATA22 DATA25 PPI0D1 PPI0D2 VDDEXT Ball No.
ADSP-BF561 Table 40. 297-Ball PBGA Ball Assignment (Alphabetically by Signal) Signal ABE0 ABE1 ABE2 ABE3 ADDR02 ADDR03 ADDR04 ADDR05 ADDR06 ADDR07 ADDR08 ADDR09 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21 ADDR22 ADDR23 ADDR24 ADDR25 AMS0 AMS1 AMS2 AMS3 AOE ARDY ARE AWE BG BGH BMODE0 BMODE1 Ball No.
ADSP-BF561 Table 40. 297-Ball PBGA Ball Assignment (Alphabetically by Signal) (Continued) Signal GND MISO MOSI NC NC NC NC NC NC NMI0 NMI1 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PF8 PF9 PF10 PF11 PF12 PF13 PF14 PF15 PPI0CLK PPI0D0 PPI0D1 PPI0D2 PPI0D3 PPI0D4 PPI0D5 PPI0D6 Ball No.
ADSP-BF561 Figure 52 lists the top view of the 297-Ball PBGA ball configura tion. Figure 53 lists the bottom view. A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF KEY: VDDINT GND NC VDDEXT I/O VROUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 TOP VIEW Figure 52.
ADSP-BF561 OUTLINE DIMENSIONS Dimensions in the outline dimension figures are shown in millimeters. 15.00 BSC SQ 17.00 BSC SQ A1 BALL PAD CORNER 1.00 BSC BALL PITCH A1 BALL PAD CORNER A B C D E F G H J K L M N P R T TOP VIEW 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BOTTOM VIEW 1.90* 1.76 1.61 SIDE VIEW DETAIL A 0.20 MAX COPLANARITY *NOTES 1. COMPLIES WITH JEDEC REGISTERED OUTLINE MO-192-AAF-1, WITH EXCEPTION TO PACKAGE HEIGHT. 2. MINIMUM BALL HEIGHT 0.45 0.45 MIN 0.70 0.60 0.
ADSP-BF561 12.10 12.00 SQ 11.90 16 15 14 13 12 11 10 9 8 A1 CORNER INDEX AREA 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T BALL A1 INDICATOR 9.75 BSC SQ TOP VIEW 0.65 BSC BOTTOM VIEW DETAIL A *1.70 1.51 1.36 DETAIL A *1.31 1.21 1.10 *0.30 NOM 0.25 MIN 0.45 COPLANARITY 0.40 0.10 MAX 0.35 BALL DIAMETER SEATING PLANE *COMPLIANT TO JEDEC STANDARDS MO-225 WITH EXCEPTION TO DIMENSIONS INDICATED BY AN ASTERISK. Figure 55.
ADSP-BF561 SURFACE-MOUNT DESIGN Table 41 is provided as an aid to PCB design. For industrystandard design recommendations, refer to IPC-7351, Generic Requirements for Surface Mount Design and Land Pattern Standard. Table 41. BGA Data for Use with Surface-Mount Design Package 256-Ball CSP_BGA (BC-256-1) 256-Ball CSP_BGA (BC-256-4) 297-Ball PBGA (B-297) Ball Attach Type Solder Mask Defined Solder Mask Defined Solder Mask Defined Solder Mask Opening 0.30 mm diameter 0.43 mm diameter 0.
ADSP-BF561 ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04696-0-9/09(E) Rev.
