Data Sheet Low Power, Precision Analog Microcontroller, Dual Sigma-Delta ADCs, Flash/EE, ARM7TDMI ADuC7060/ADuC7061 FEATURES Analog input/output Dual (24-bit) ADCs Single-ended and differential inputs Programmable ADC output rate (4 Hz to 8 kHz) Programmable digital filters Built-in system calibration Low power operation mode Primary (24-bit) ADC channel 2 differential pairs or 4 single-ended channels PGA (1 to 512) input stage Selectable input range: ±2.34 mV to ±1.
ADuC7060/ADuC7061 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Flash/EE Memory Reliability .................................................... 58 Applications ....................................................................................... 1 Programming .............................................................................. 58 General Description ....................................................
Data Sheet ADuC7060/ADuC7061 REVISION HISTORY 6/09—Rev. 0 to Rev. A 4/12—Rev. C to Rev. D Changes to Table 1 ............................................................................ 6 Changes to Table 7 ..........................................................................14 Changes to Table 16 ........................................................................25 Change to Command Sequence for Executing a Mass Erase Section ...................................................................
ADuC7060/ADuC7061 Data Sheet FUNCTIONAL BLOCK DIAGRAM PRECISION ANALOG PERIPHERALS ADC0 ADC1 POR MUX PGA 24-BIT Σ-Δ ADC ARM7TDMI MCU ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 MUX BUF 10MHz ON-CHIP OSC (3%) PLL 4× TIMERS WDT W/U TIMER PWM GPIO PORT UART PORT SPI PORT I2C PORT 24-BIT Σ-Δ ADC PRECISION REFERENCE IEXC0 IEXC1 DAC0 BUF 14-BIT DAC MEMORY 32kB FLASH 4kB RAM TEMP SENSOR VREF+ RESET XTALI XTALO VIC (VECTORED INTERRUPT CONTROLLER) ADuC7060/ ADuC7061 Figure 1. Rev.
Data Sheet ADuC7060/ADuC7061 SPECIFICATIONS ELECTRICAL SPECIFICATIONS VDD = 2.5 V ± 5%, VREF+ = 1.2 V, VREF− = GND, fCORE = 10.24 MHz driven from an external 32.768 kHz watch crystal or on-chip oscillator, all specifications TA = −40°C to +125°C, unless otherwise noted. Output noise specifications can be found in Table 36 (primary ADC) and Table 38 (ADC auxiliary channel). Table 1.
ADuC7060/ADuC7061 Parameter ADC SPECIFICATIONS: ANALOG INPUT Main Channel Absolute Input Voltage Range Input Voltage Range (Differential Voltage Between AIN+ and AIN–) Common Mode Voltage, VCM 10 Input Leakage Current1 Common-Mode Rejection DC1 On ADC Input Common-Mode Rejection 50 Hz/60 Hz1 Normal-Mode Rejection 50 Hz/60 Hz1 On ADC Input Auxiliary Channel Absolute Input Voltage Range1 Input Voltage Range Common-Mode Rejection DC1 On ADC Input Common-Mode Rejection 50 Hz/60 Hz1 Normal-Mode Rejection 50
Data Sheet Parameter External Reference Input Range 12 VREF Divide-by-2 Initial Error1 DAC CHANNEL SPECIFICATIONS Voltage Range DAC 12-BIT MODE DC Specifications 13 Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error ADuC7060/ADuC7061 Test Conditions/Comments Min 0.1 Typ 0.1 0 0 TEMPERATURE SENSOR1, 15 Accuracy Voltage Output at 0°C Voltage Tempco Thermal Impedance POWER-ON RESET (POR) POR Trip Level1 RESET Timeout from POR % VREF AVDD − 0.2 V V ±1 ±15 ±1 ±1 0.
ADuC7060/ADuC7061 Parameter EXCITATION CURRENT SOURCES Output Current Initial Tolerance at 25°C Drift1 Initial Current Matching at 25°C Drift Matching1 Line Regulation (AVDD)1 Output Compliance1 WATCHDOG TIMER (WDT) Timeout Period1 Timeout Step Size FLASH/EE MEMORY1 Endurance 16 Data Retention 17 DIGITAL INPUTS Input Leakage Current Input Pull-Up Current Input Capacitance Input Leakage Current Input Pull-Down Current LOGIC INPUTS1 Input Low Voltage (VINL) Input High Voltage (VINH) LOGIC OUTPUTS1 Output Low
Data Sheet Parameter POWER REQUIREMENTS Power Supply Voltages DVDD (±5%) AVDD (±5%) Power Consumption IDD (MCU Normal Mode) 18 IDD (MCU Powered Down)1 IDD (Primary ADC) IDD (Auxiliary ADC) IDD (DAC) PWM ADuC7060/ADuC7061 Test Conditions/Comments Min Typ Max Unit 2.375 2.375 2.5 2.5 2.625 2.625 V V 6 10 mA 3.1 2.74 mA mA 350 120 µA µA MCU clock rate = 10.
ADuC7060/ADuC7061 Data Sheet TIMING SPECIFICATIONS I2C Timing Table 2. I2C® Timing in Standard Mode (100 kHz) Parameter tL tH tSHD tDSU tDHD tRSU tPSU tBUF tR tF Slave Min Max 4.7 4.0 4.0 250 0 3.45 4.7 4.0 4.
Data Sheet ADuC7060/ADuC7061 SPI Timing Table 3.
ADuC7060/ADuC7061 Data Sheet SCLOCK (POLARITY = 0) tSH tSL tSR tSF SCLOCK (POLARITY = 1) tDAV tDOSU MOSI tDF tDR MSB MISO BITS 6 TO 1 MSB IN LSB BITS 6 TO 1 LSB IN 07079-031 tDSU tDHD Figure 4. SPI Master Mode Timing (Phase Mode = 0) Table 5.
Data Sheet ADuC7060/ADuC7061 Table 6.
ADuC7060/ADuC7061 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = −40°C to +125°C, unless otherwise noted. Table 7. Parameter AGND to DGND to AVDD to DVDD Digital I/O Voltage to DGND VREF± to AGND ADC Inputs to AGND ESD (Human Body Model) Rating All Pins Storage Temperature Junction Temperature Transient Continuous Lead Temperature Soldering Reflow (15 sec) Rating −0.3 V to +0.3 V −0.3 V to +3.6 V −0.3 V to AVDD + 0.3 V −0.3 V to AVDD + 0.
Data Sheet ADuC7060/ADuC7061 48 47 46 45 44 43 42 41 40 39 38 37 TCK TDI TDO NTRST/BM DVDD DGND P2.1/IRQ3/PWM5 P1.6/PWM4 P1.5/PWM3 P1.4/PWM2 P2.0/IRQ2/PWM0/EXTCLK P0.4/IRQ0/PWM1 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR ADuC7060 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 XTALI XTALO P0.3/MOSI/SDA P0.2/MISO P0.1/SCLK/SCL P0.0/SS DVDD DGND ADC9 ADC8 ADC7 ADC6 NOTES 1. THE LFCSP_VQ ONLY HAS AN EXPOSED PADDLE THAT MUST BE LEFT UNCONNECTED.
ADuC7060/ADuC7061 Data Sheet Pin No. 12 Mnemonic ADC5/EXT_REF2IN− Type 1 I 13 ADC4/EXT_REF2IN+ I 14 15 16 17 18 ADC3 ADC2 IEXC1 IEXC0 GND_SW I I O O I 19 ADC1 I 20 ADC0 I 21 22 23 24 25 26 27 28 29 30 31 VREF+ VREF− AGND AVDD ADC6 ADC7 ADC8 ADC9 DGND DVDD P0.0/SS I I S S I I I I S S I/O 32 P0.1/SCLK/SCL I/O 33 P0.2/MISO I/O 34 P0.3/MOSI/SDA I/O 35 36 37 XTALO XTALI P0.4/IRQ0/PWM1 O I I/O 38 P2.0/IRQ2/PWM0/EXTCLK I/O 39 P1.4/PWM2 I/O 40 P1.5/PWM3 I/O 41 P1.
Data Sheet ADuC7060/ADuC7061 Pin No. 43 44 45 Mnemonic DGND DVDD NTRST/BM Type 1 S S I 46 47 TDO TDI O I 48 TCK I 1 Description Digital Ground. Digital Supply Pin. JTAG Reset/Boot Mode. Input pin used for debug and download only and boot mode (BM). The ADuC7060 enters serial download mode if BM is low at reset and executes code if BM is pulled high at reset through a 13 kΩ resistor. JTAG Data Out. Output pin used for debug and download only. JTAG Data In.
Data Sheet 32 31 30 29 28 27 26 25 TCK TDI TDO NTRST/BM DVDD DGND P2.0/IRQ2/PWM0 P0.4/IRQ0/PWM1 ADuC7060/ADuC7061 1 2 3 4 5 6 7 8 PIN 1 INDICATOR ADuC7061 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 XTALI XTALO P0.3/MOSI/SDA/ADC9 P0.2/MISO/ADC8 P0.1/SCLK/SCL/ADC7 P0.0/SS/ADC6 VREF– VREF+ NOTES 1. THE 32-LEAD LFCSP_VQ HAS AN EXPOSED PADDLE. THIS EXPOSED PADDLE MUST BE LEFT UNCONNECTED. 07079-003 ADC2 IEXC1 IEXC0 GND_SW ADC1 ADC0 AGND AVDD 9 10 11 12 13 14 15 16 RESET TMS P1.0/IRQ1/SIN/T0 P1.
Data Sheet ADuC7060/ADuC7061 Pin No. 21 Mnemonic P0.2/MISO/ADC8 Type 1 I/O 22 P0.3/MOSI/SDA/ADC9 I/O 23 24 25 XTALO XTALI P0.4/IRQ0/PWM1 O I I/O 26 P2.0/IRQ2/PWM0 I/O 27 28 29 DGND DVDD NTRST/BM S S I 30 31 TDO TDI O I 32 TCK I 1 Description General-Purpose Input and General-Purpose Output P0.2/SPI Master Input Slave Output/Auxiliary ADC8 Input. This is a triple function input/output pin. Single-ended or differential Analog Input 8. Analog input for the auxiliary ADC.
ADuC7060/ADuC7061 Data Sheet TERMINOLOGY Conversion Rate The conversion rate specifies the rate at which an output result is available from the ADC, when the ADC has settled. The sigma-delta (Σ-Δ) conversion techniques used on this part mean that whereas the ADC front-end signal is oversampled at a relatively high sample rate, a subsequent digital filter is used to decimate the output, giving a valid 24-bit data conversion result at output rates from 1 Hz to 8 kHz.
Data Sheet ADuC7060/ADuC7061 OVERVIEW OF THE ARM7TDMI CORE The ARM7® core is a 32-bit, reduced instruction set computer (RISC), developed by ARM® Ltd. The ARM7TDMI is a von Neumann-based architecture, meaning that it uses a single 32-bit bus for instruction and data. The length of the data can be 8, 16, or 32 bits, and the length of the instruction word is either 16 bits or 32 bits, depending on the mode in which the core is operating.
ADuC7060/ADuC7061 Data Sheet such as C, it is necessary to ensure that the stack does not overflow. This is dependent on the performance of the compiler that is used. When an exception occurs, some of the standard registers are replaced with registers specific to the exception mode. All exception modes have replacement banked registers for the stack pointer (R13) and the link register (R14) as represented in Figure 9. The FIQ mode has more registers (R8 to R12) supporting faster interrupt processing.
Data Sheet ADuC7060/ADuC7061 By default, after a reset, the Flash/EE memory is logically mapped to Address 0x00000000. It is possible to logically remap the SRAM to Address 0x00000000 by setting Bit 0 of the remap MMR located at 0xFFFF0220. To revert Flash/EE to 0x00000000, Bit 0 of remap is cleared. It is sometimes desirable to remap RAM to 0x00000000 to optimize the interrupt latency of the ADuC706x because code can run in full 32-bit ARM mode and at maximum core speed.
ADuC7060/ADuC7061 FEECON Register FEECON is an 8-bit command register. The commands are described in Table 15. Data Sheet Name: FEECON Address: 0xFFFF0E08 Default value: 0x07 Access: Read and write Table 15.
Data Sheet ADuC7060/ADuC7061 FEEDAT Register FEEHIDE Register FEEDAT is a 16-bit data register. This register holds the data value for flash read and write commands. The FEEHIDE MMR provides immediate protection. It does not require any software key. Note that the protection settings in FEEHIDE are cleared by a reset (see Table 16).
ADuC7060/ADuC7061 Data Sheet Permanent Protection Command Sequence for Executing a Mass Erase Permanent protection can be set via FEEPRO, similar to how keyed permanent protection is set, with the only difference being that the software key used is 0xDEADDEAD. When the FEEPRO write sequence is saved, only a mass erase sets the software protection key back to 0xFFFFFFFF. This also erases the entire user code space.
Data Sheet ADuC7060/ADuC7061 MEMORY MAPPED REGISTERS 0xFFFFFFFF The memory mapped register (MMR) space is mapped into the upper two pages of the memory array and is accessed by indirect addressing through the ARM7 banked registers. 0xFFFF0FC0 The access time for reading from or writing to an MMR depends on the advanced microcontroller bus architecture (AMBA) bus used to access the peripheral.
ADuC7060/ADuC7061 Data Sheet COMPLETE MMR LISTING In the following MMR tables, addresses are listed in hexadecimal code. Access types include R for read, W for write, and R/W for read and write. Table 17.
Data Sheet ADuC7060/ADuC7061 Table 19.
ADuC7060/ADuC7061 Data Sheet Table 21.
Data Sheet ADuC7060/ADuC7061 Table 24.
ADuC7060/ADuC7061 Data Sheet Table 27. Flash/EE Base Address = 0xFFFF0E00 Address 0x0E00 0x0E04 0x0E08 0x0E0C 0x0E10 0x0E18 0x0E1C 0x0E20 Name FEESTA FEEMOD FEECON FEEDAT FEEADR FEESIGN FEEPRO FEEHIDE Bytes 2 2 1 2 2 3 4 4 Access Type R R/W R/W R/W R/W R R/W R/W Default Value 0x20 0x0000 0x07 0xXXXX 0x0000 0xFFFFFF 0x00000000 0xFFFFFFFF Description Flash/EE status MMR. Flash/EE control MMR. Flash/EE control MMR. Flash/EE data MMR. Flash/EE address MMR. Flash/EE LFSR MMR. Flash/EE protection MMR.
Data Sheet ADuC7060/ADuC7061 RESET RSTCLR Register There are four kinds of resets: external reset, power-on reset, watchdog reset, and software reset. The RSTSTA register indicates the source of the last reset and can be written by user code to initiate a software reset event. Name: RSTCLR Address: 0xFFFF0234 Access: Write only Function: This 8-bit write only register clears the corresponding bit in RSTSTA.
ADuC7060/ADuC7061 Data Sheet OSCILLATOR, PLL, AND POWER CONTROL CLOCKING SYSTEM In case of crystal loss, the watchdog timer should be used. During initialization, a test on the RSTSTA can determine if the reset came from the watchdog timer. The ADuC706x integrates a 32.768 kHz ±3% oscillator, a clock divider, and a PLL. The PLL locks onto a multiple of the internal oscillator or an external 32.768 kHz crystal to provide a stable 10.24 MHz clock (UCLK) for the system.
Data Sheet ADuC7060/ADuC7061 By writing to POWCON1, it is possible to further reduce power consumption in active mode by powering down the UART, PWM or I2C/SPI blocks. To access POWCON1, POWKEY3 must be set to 0x76 in the instruction immediately before accessing POWCON1 and POWKEY4 must be set to 0xB1 in the instruction immediately after. For example, the following code enables the SPI/I2C blocks but, powers down the PWM and UART blocks.
ADuC7060/ADuC7061 Data Sheet POWKEY2 Register POWCON1 Register Name: POWKEY2 Name: POWCON1 Address: 0xFFFF040C Address: 0xFFFF0438 Default value: 0xXXXX Default value: 0x124 Access: Write Access: Read and write Function: When writing to POWCON0, the value of 0xF4 must be written to this register in the instruction immediately before writing to POWCON0. Function: This register controls the clock signal to the PWM, UART and I2C/SPI blocks.
Data Sheet ADuC7060/ADuC7061 Table 34. Typical Current Consumption at 25°C in mA 1 POWCON0[6:3] 1111 1110 1100 1000 0000 Mode Active 2 Pause 3 Nap3 Sleep3 Stop3 CD = 0 5.22 2.6 1.33 0.085 0.055 CD = 1 4.04 1.95 1.29 0.085 0.055 CD = 2 2.69 1.6 1.29 0.085 0.055 CD = 3 2.01 1.49 1.29 0.085 0.055 CD = 4 1.67 1.4 1.29 0.085 0.055 CD = 5 1.51 1.33 1.29 0.085 0.055 CD = 6 1.42 1.31 1.29 0.085 0.055 CD = 7 1.38 1.3 1.29 0.085 0.
ADuC7060/ADuC7061 Data Sheet ADC CIRCUIT INFORMATION AVDD INTERNAL REFERENCE IEXC0 VREF+ VREF– DAC0 BUF DAC CONVERSION COUNTER AVDD IEXC1 50µA O/C DETECT ADC0 AUX_REFP OVERRANGE AUX_REFM ADC1 0.5Hz TO 8kHz Σ-∆ MODULATOR PROGRAMMABLE FILTER PGA CHOP MUX 0.2mA TO 1mA 0.
Data Sheet ADuC7060/ADuC7061 Table 36. Primary ADC—Typical Output RMS Noise in Normal Mode (μV) ADC Register Status Chop On Chop Off Chop Off Chop Off Data Update Rate 4 Hz 50 Hz 1 kHz 8 kHz ±1.2 V (PGA = 1) 0.62 μV 1.97 μV 8.54 μV 54.97 μV ±600 mV (PGA = 2) 0.648 μV 1.89 μV 8.4 μV 55.54 μV ±300 mV (PGA = 4) 0.175 μV 0.570 μV 2.55 μV 14.30 μV ±150 mV (PGA = 8) 0.109 μV 0.38 μV 1.6 μV 7.88 μV Input Voltage Noise (mV) ±75 mV ±37.5 mV ±18.75 mV (PGA = 16) (PGA = 32) (PGA = 64) 0.077 μV 0.041 μV 0.
ADuC7060/ADuC7061 Data Sheet Table 39. Example Scenarios for Using Diagnostic Current Sources Diagnostic Test Register Setting ADC0DIAG[1:0] = 0 Description Convert ADC0/ADC1 as normal with diagnostic currents disabled. Normal Result Expected differential result across ADC0/ADC1. Fault Result Short circuit. ADC0DIAG[1:0] = 1 Enable a 50 μA diagnostic current source on ADC0 by setting ADC0DIAG[1:0] = 1. Convert ADC0 and ADC1. Main ADC changes by ΔV = +50 μA × R1. For example, ~100 mV for R1 = 2 kΩ.
Data Sheet ADuC7060/ADuC7061 ADC COMPARATOR AND ACCUMULATOR ADC MMR INTERFACE Every primary ADC result can be compared to a preset threshold level (ADC0TH) as configured via ADCCFG[4:3]. An MCU interrupt is generated if the absolute (sign independent) value of the ADC result is greater than the preprogrammed comparator threshold level.
ADuC7060/ADuC7061 Data Sheet Table 40. ADCSTA MMR Bit Designations Bit 15 Name ADCCALSTA 14 13 ADC1CERR 12 ADC0CERR 11:7 6 ADC0ATHEX 5 4 ADC0THEX 3 ADC0OVR 2 1 ADC1RDY 0 ADC0RDY Description ADC calibration status. This bit is set automatically in hardware to indicate that an ADC calibration cycle has been completed. This bit is cleared after ADCMDE is written to. Not used. This bit is reserved for future functionality. Auxiliary ADC conversion error.
Data Sheet ADuC7060/ADuC7061 ADC Interrupt Mask Register Name: ADCMSKI Address: 0xFFFF0504 Default value: 0x0000 Access: Read and write Function: This register allows the ADC interrupt sources to be enabled individually. The bit positions in this register are the same as the lower eight bits in the ADCSTA MMR. If a bit is set by user code to 1, the respective interrupt is enabled. By default, all bits are 0, meaning all ADC interrupt sources are disabled. Table 41.
ADuC7060/ADuC7061 Bit 4:3 Name ADCLPMCFG[1:0] 2:0 ADCMD[2:0] Data Sheet Description ADC power mode configuration. [00] = ADC normal mode. If enabled, the ADC operates with normal current consumption yielding optimum electrical performance. [01] = ADC low power mode. [10] = ADC normal mode, same as [00]. [11] = ADC low power plus mode (low power mode and PGA off ). ADC operation mode configuration. [000] = ADC power-down mode. All ADC circuits and the input amplifier are powered down.
Data Sheet ADuC7060/ADuC7061 Table 43. ADC0CON MMR Bit Designations Bit 15 Name ADC0EN 14:13 ADC0DIAG[1:0] 12 HIGHEXTREF0 11 AMP_CM 10 ADC0CODE 9:6 ADC0CH[3:0] 5:4 ADC0REF[1:0] 3:0 ADC0PGA[3:0]. Description Primary channel ADC enable. This bit is set to 1 by user code to enable the primary ADC. Clearing this bit to 0 powers down the primary ADC and resets the respective ADC ready bit in the ADCSTA MMR to 0. Diagnostic current source enable bits. [00] = current sources off.
ADuC7060/ADuC7061 Data Sheet Auxiliary ADC Control Register Name: ADC1CON Address: 0xFFFF0510 Default value: 0x0000 Access: Read and write Function: The auxiliary ADC control MMR is a 16-bit register. Table 44. ADC1CON MMR Bit Designations Bit 15 Name ADC1EN 14:13 ADC1DIAG[1:0] 12 HIGHEXTREF1 11 ADC1CODE 10:7 ADC1CH[3:0] Description Auxiliary channel ADC enable. This bit is set to 1 by user code to enable the auxiliary ADC. Clearing this bit to 0 powers down the auxiliary ADC.
Data Sheet ADuC7060/ADuC7061 Bit 6:4 Name ADC1REF[2:0] 3:2 BUF_BYPASS[1:0] 1:0 Description Auxiliary channel ADC reference select. [000] = internal reference selected. In ADC low power mode, the voltage reference selection is controlled by ADCMODE[5]. [001] = external reference inputs (VREF+, VREF−) selected. Set the HIGHEXTREF1 bit if reference voltage exceeds 1.3 V. [010] = auxiliary external reference inputs (ADC4/EXT_REF2IN+, ADC5/EXT_REF2IN−) selected.
ADuC7060/ADuC7061 Bit 7 Name NOTCH2 6:0 SF[6:0] Data Sheet Description Sinc3 modify. Set by user to modify the standard sinc3 frequency response to increase the filter stop-band rejection by approximately 5 dB. This is achieved by inserting a second notch (NOTCH2) at fNOTCH2 = 1.333 × fNOTCH where fNOTCH is the location of the first notch in the response. Sinc3 decimation factor (SF). 1 The value (SF) written in these bits controls the oversampling (decimation factor) of the sinc3 filter.
Data Sheet ADuC7060/ADuC7061 ADC Configuration Register Name: ADCCFG Address: 0xFFFF0518 Default value: 0x00 Access: Read and write Function: The 8-bit ADC configuration MMR controls extended functionality related to the on-chip ADCs. Table 48. ADCCFG MMR Bit Designations Bit 7 Name GNDSW_EN 6:5 ADC0ACCEN[1:0] 4:3 ADC0CMPEN[1:0] 2 ADC0OREN 1 GNDSW_RES_EN 0 ADCRCEN Description Analog ground switch enable.
ADuC7060/ADuC7061 Data Sheet Primary Channel ADC Data Register Primary Channel ADC Offset Calibration Register Name: ADC0DAT Name: ADC0OF Address: 0xFFFF051C Address: 0xFFFF0524 Default value: 0x00000000 Default value: Part specific, factory programmed Access: Read only Access: Read and write Function: This ADC data MMR holds the 24-bit conversion result from the primary ADC. The ADC does not update this MMR if the ADC0 conversion result ready bit (ADCSTA[0]) is set.
Data Sheet ADuC7060/ADuC7061 Table 52. ADC1OF MMR Bit Designations Primary Channel ADC Result Counter Limit Register Bit 15:0 Name: ADC0RCR Address: 0xFFFF0534 Description ADC1 16-bit offset calibration value.
ADuC7060/ADuC7061 Data Sheet Primary Channel ADC Threshold Register Primary Channel ADC Threshold Counter Register Name: ADC0TH Name: ADC0THV Address: 0xFFFF053C Address: 0xFFFF0544 Default value: 0x0000 Default value: 0x0000 Access: Read and write Access: Read only Function: This 16-bit MMR sets the threshold against which the absolute value of the primary ADC conversion result is compared.
Data Sheet ADuC7060/ADuC7061 Primary Channel ADC Comparator Threshold Register Table 61. ADC0ATH MMR Bit Designations Name: ADC0ATH Address: 0xFFFF054C Bit 31:0 Default value: 0x00000000 Access: Read and write Function: This 32-bit MMR holds the threshold value for the accumulator comparator of the primary channel. When the accumulator value in ADC0ACC exceeds the value in ADC0ATH, the ADC0ATHEX bit in ADCSTA is set. This causes an interrupt if the corresponding bit in ADCMSKI is also enabled.
ADuC7060/ADuC7061 Data Sheet Excitation Current Sources Control Register Name: IEXCON Address: 0xFFFF0570 Default value: 0x00 Access: Read and write Function: This 8-bit MMR controls the two excitation current sources, IEXC0 and IEXC1. Table 62. IEXCON MMR Bit Designations Bit 7 Name IEXC1_EN 6 IEXC0_EN 5 IEXC1_DIR 4 IEXC0_DIR 3:1 IOUT[3:1] 0 IOUT[0] Description Enable bit for IEXC1 current source. Set this bit to 1 to enable Excitation Current Source 1.
Data Sheet ADuC7060/ADuC7061 ADuC7060/ ADuC7061 ADuC7060/ ADuC7061 +2.5V +2.5V AVDD/DVDD IEXC1 AVDD/DVDD VREF+ ADC0 SPI I 2C UART GPIO ADC0 ADC1 RTD ADC1 SPI I 2C UART GPIO VREF– AGND/DGND VREF– Figure 18. Bridge Interface Circuit Figure 20. Example of an RTD Interface Circuit ADuC7060/ ADuC7061 +2.5V ADC0 AVDD/DVDD ADC1 ADC4 ADR280 VREF+ VREF– AGND/DGND 07079-013 AD592 SPI I2 C UART GPIO Figure 19. Example of a Thermocouple Interface Circuit Rev.
ADuC7060/ADuC7061 Data Sheet DAC PERIPHERALS DAC Op Amp Mode The ADuC706x incorporates a voltage output DAC on chip. In normal mode, the DAC resolution is 12-bits. In interpolation, the DAC resolution is 16 bits with 14 effective bits. The DAC has a rail-to-rail voltage output buffer capable of driving 5 kΩ/100 pF. As an option, the DAC can be disabled and its output buffer used as an op amp. MMR INTERFACE The DAC has four selectable ranges.
Data Sheet ADuC7060/ADuC7061 DAC0DAT Register Name: DAC0DAT Address: 0xFFFF0604 Default value: 0x00000000 Access: Read and write Function: This 32-bit MMR contains the DAC output value. Table 64. DAC0DAT MMR Bit Designations Bit 31:28 27:16 15:12 11:0 Description Reserved. 12-bit data for DAC0. Extra four bits used in interpolation mode. Reserved. Code 4095.
ADuC7060/ADuC7061 Data Sheet NONVOLATILE FLASH/EE MEMORY Overall, Flash/EE memory represents a step closer to the ideal memory device that includes nonvolatility, in-circuit programmability, high density, and low cost. Incorporated in the ADuC706x, Flash/EE memory technology allows the user to update program code space in-circuit, without the need to replace one time programmable (OTP) devices at remote operating nodes. The ADuC706x contains a 32 kB array of Flash/EE memory.
Data Sheet ADuC7060/ADuC7061 PROCESSOR REFERENCE PERIPHERALS INTERRUPT SYSTEM IRQ There are 15 interrupt sources on the ADuC706x that are controlled by the interrupt controller. All interrupts are generated from the on-chip peripherals, except for the software interrupt (SWI), which is programmable by the user. The ARM7TDMI CPU core recognizes interrupts as one of two types only: a normal interrupt request (IRQ) or a fast interrupt request (FIQ). All the interrupts can be masked separately.
ADuC7060/ADuC7061 Data Sheet IRQCLR Register FIQSIG Register Name: IRQCLR Name: FIQSIG Address: 0xFFFF000C Address: 0xFFFF0104 Default value: 0x00000000 Default value: Undefined Access: Write only Access: Read only IRQSTA FIQEN IRQSTA is a read-only register that provides the current enabled IRQ source status (effectively a logic AND of the IRQSIG and IRQEN bits). When set to 1, that source generates an active IRQ request to the ARM7TDMI core.
Data Sheet ADuC7060/ADuC7061 FIQSTA Register Name: FIQSTA Address: 0xFFFF0100 Default value: 0x00000000 Access: Read only • Vectored interrupts—allows a user to define separate interrupt service routine addresses for every interrupt source. This is achieved by using the IRQBASE and IRQVEC registers. • IRQ/FIQ interrupts—can be nested up to eight levels depending on the priority settings. An FIQ still has a higher priority than an IRQ.
ADuC7060/ADuC7061 Data Sheet Table 68. IRQVEC MMR Bit Designations Bit 31:23 22:7 6:2 1:0 Access Read only Read only Read only Reserved IRQP1 Register Initial Value 0 Description Always read as 0. Name: IRQP1 Address: 0xFFFF0024 0 IRQBASE register value. Default value: 0x00000000 0 Highest priority IRQ source. This is a value between 0 to 19 representing the possible interrupt sources. For example, if the highest currently active IRQ is Timer1, then these bits are [01000]. Reserved bits.
Data Sheet ADuC7060/ADuC7061 IRQCONN IRQSTAN Register The IRQCONN register is the IRQ and FIQ control register. It contains two active bits: the first to enable nesting and prioritization of IRQ interrupts, and the other to enable nesting and prioritization of FIQ interrupts. Name: IRQSTAN Address: 0xFFFF003C Default value: 0x00000000 Access: Read and write If these bits are cleared, FIQs and IRQs can still be used, but it is not possible to nest IRQs or FIQs.
ADuC7060/ADuC7061 Data Sheet FIQSTAN External Interrupts (IRQ0 to IRQ3) If IRQCONN[1] is asserted and FIQVEC is read, then one of these bits asserts. The bit that asserts depends on the priority of the FIQ. If the FIQ is of Priority 0, Bit 0 asserts; Priority 1, Bit 1 asserts; and so forth. The ADuC706x provides up to four external interrupt sources. These external interrupts can be individually configured as level triggered or rising/falling edge triggered.
Data Sheet ADuC7060/ADuC7061 IRQCLRE Register Table 77. IRQCLRE MMR Bit Designations Name: IRQCLRE Bit 31:20 Name Reserved Address: 0xFFFF0038 Default value: 0x00000000 19 IRQ3CLRI Access: Read and write 18 IRQ2CLRI 17:15 Reserved 14 IRQ1CLRI 13 IRQ0CLRI 12:0 Reserved Rev. D | Page 65 of 108 Description These bits are reserved and should not be written to. A 1 must be written to this bit in the IRQ3 interrupt service routine to clear an edge triggered IRQ3 interrupt.
ADuC7060/ADuC7061 Data Sheet TIMERS The ADuC706x features four general-purpose timer/counters. • • • • Timer0 Timer1 or wake-up timer Timer2 or watchdog timer Timer3 The four timers in their normal mode of operation can be either free running or periodic. In free running mode, the counter decrements/increments from the maximum or minimum value until zero/full scale and starts again at the maximum or minimum value.
Data Sheet ADuC7060/ADuC7061 TIMER0 Timer0 Load Registers Timer0 is a 32-bit, general-purpose timer, count down or count up, with a programmable prescaler. The prescaler source can be the low power 32.768 kHz oscillator, the core clock, or from one of two external GPIOs. This source can be scaled by a factor of 1, 16, 256, or 32,768. This gives a minimum resolution of 97.66 ns with a prescaler of 1 (ignoring the external GPIOs).
ADuC7060/ADuC7061 Data Sheet Timer0 Capture Register Name: T0CAP Address: 0xFFFF0330 Default value: 0x00000000 Access: Read only Function: This 32-bit register holds the 32-bit value captured by an enabled IRQ event. Timer0 Control Register Name: T0CON Address: 0xFFFF0328 Default value: 0x01000000 Access: Read and write Function: This 32-bit MMR configures the mode of operation of Timer0. Table 80.
Data Sheet Bit 5:4 Name T0FORMAT 3:0 T0SCALE ADuC7060/ADuC7061 Description Format. [00] = binary (default). [01] = reserved. [10] = hours:minutes:seconds:hundredths (23 hours to 0 hours). [11] = hours:minutes:seconds:hundredths (255 hours to 0 hours). Prescaler. [0000] = source clock/1 (default). [0100] = source clock/16. [1000] = source clock/256. [1111] = source clock/32,768. Note that all other values are undefined.
ADuC7060/ADuC7061 Data Sheet 32-BIT LOAD 32.768kHz OSCILLATOR CORE CLOCK PRESCALER 1, 16, 256, OR 32,768 32-BIT UP/DOWN COUNTER EXTERNAL 32.768kHz WATCH CRYSTAL TIMER1 VALUE TIMER1 IRQ 07079-018 CORE CLOCK FREQUENCY/CD Figure 24. Timer1 Block Diagram Timer1 Control Register Name: T1CON Address: 0xFFFF0348 Default value: 0x0000 Access: Read and write Function: This 16-bit MMR configures the mode of operation of Timer1. Table 81.
Data Sheet ADuC7060/ADuC7061 TIMER2 OR WATCHDOG TIMER Timer2 Interface Timer2 has two modes of operation, normal mode and watchdog mode. The watchdog timer is used to recover from an illegal software state. When enabled, it requires periodic servicing to prevent it from forcing a reset of the processor. The Timer2 interface consists of four MMRs. • • • Timer2 reloads the value from T2LD either when Timer2 overflows or immediately when T2CLRI is written.
ADuC7060/ADuC7061 Data Sheet Timer2 Control Register Name: T2CON Address: 0xFFFF0368 Default value: 0x0000 Access: Read and write Function: This 16-bit MMR configures the mode of operation of Timer2, as described in detail in Table 82. Table 82. T2CON MMR Bit Designations Bit 15:9 8 Name T2DIR 7 T2EN 6 T2MOD 5 WDOGMDEN 4 3:2 T2SCALE 1 WDOGENI 0 T2PDOFF Description Reserved. These bits are reserved and should be written as 0 by user code. Count up/count down enable.
Data Sheet ADuC7060/ADuC7061 TIMER3 Timer3 Value Register Timer3 is a general-purpose, 16-bit, count up/count down timer with a programmable prescaler. Timer3 can be clocked from the core clock or the low power 32.768 kHz oscillator with a prescaler of 1, 16, 256, or 32,768. Name: T3VAL Address: 0xFFFF0384 Default value: 0xFFFF Access: Read only Function: T3VAL is a 16-bit register that holds the current value of Timer3.
ADuC7060/ADuC7061 Data Sheet Table 83. T3CON MMR Bit Designations Bit 31:18 17 Name 16:12 11 10:9 T3CAPSEL 8 T3DIR 7 T3EN 6 T3MOD 5:4 3:0 T3SCALE T3CAPEN T3CLKSEL Description Reserved. Event enable bit. Set by user to enable time capture of an event. Cleared by user to disable time capture of an event. Event select range, 0 to 17. The events are described in Table 78. Reserved. Clock select. [00] = 32.768 kHz oscillator. [01] = 10.24 MHz/CD. [10] = 10.24 MHz. [11] = reserved. Count up.
Data Sheet ADuC7060/ADuC7061 PULSE-WIDTH MODULATOR PULSE-WIDTH MODULATOR GENERAL OVERVIEW Each ADuC706x integrates a 6-channel pulse-width modulator (PWM) interface. The PWM outputs can be configured to drive an H-bridge or can be used as standard PWM outputs. On power-up, the PWM outputs default to H-bridge mode. This ensures that the motor is turned off by default. In standard PWM mode, the outputs are arranged as three pairs of PWM pins.
ADuC7060/ADuC7061 Data Sheet Table 85. PWMCON MMR Bit Designations Bit 15 14 Name Reserved Sync 13 PWM5INV 12 PWM3INV 11 PWM1INV 10 PWMTRIP 9 ENA 8:6 PWMCP[2:0] 5 POINV 4 HOFF 3 LCOMP 2 DIR 1 HMODE 0 PWMEN 1 Description This bit is reserved. Do not write to this bit. Enables PWM synchronization. Set to 1 by user so that all PWM counters are reset on the next clock edge after the detection of a high-to-low transition on the P1.2/SYNC pin.
Data Sheet ADuC7060/ADuC7061 On power-up, PWMCON defaults to 0x0012 (HOFF = 1 and HMODE = 1). All GPIO pins associated with the PWM are configured in PWM mode by default (seeTable 86). Clear the PWM trip interrupt by writing any value to the PWMCLRI MMR. Note that when using the PWM trip interrupt, clear the PWM interrupt before exiting the ISR. This prevents generation of multiple interrupts. Table 86.
ADuC7060/ADuC7061 Data Sheet PWM0COM0 Compare Register PWM1COM0 Compare Register Name: PWM0COM0 Name: PWM1COM0 Address: 0xFFFF0F84 Address: 0xFFFF0F94 Default value: 0x0000 Default value: 0x0000 Access: Read and write Access: Read and write Function: PWM0 output pin goes high when the PWM timer reaches the count value stored in this register. Function: PWM2 output pin goes high when the PWM timer reaches the count value stored in this register.
Data Sheet ADuC7060/ADuC7061 PWM2COM0 Compare Register PWM2LEN Register Name: PWM2COM0 Name: PWM2LEN Address: 0xFFFF0FA4 Address: 0xFFFF0FB0 Default value: 0x0000 Default value: 0x0000 Access: Read and write Access: Read and write Function: PWM4 output pin goes high when the PWM timer reaches the count value stored in this register. Function: PWM5 output pin goes high when the PWM timer reaches the value stored in this register.
ADuC7060/ADuC7061 Data Sheet UART SERIAL INTERFACE Each ADuC706x features a 16450-compatible UART. The UART is a full-duplex, universal, asynchronous receiver/transmitter. A UART performs serial-to-parallel conversion on data characters received from a peripheral device and parallel-to-serial conversion on data characters received from the ARM7TDMI. The UART features a fractional divider that facilitates high accuracy baud rate generation and a network addressable mode.
Data Sheet ADuC7060/ADuC7061 UART Transmit Register UART Divisor Latch Register 1 Write to this 8-bit register (COMTX) to transmit data using the UART. This 8-bit register contains the most significant byte of the divisor latch that controls the baud rate at which the UART operates. COMTX Register Name: COMTX Address: 0xFFFF0700 Access: Write only COMDIV1 Register UART Receive Register This 8-bit register (COMRX) is read to receive data transmitted using the UART.
ADuC7060/ADuC7061 Data Sheet Table 90. COMCON0 MMR Bit Designations Bit 7 Name DLAB 6 BRK 5 SP 4 EPS 3 PEN 2 Stop 1:0 WLS Description Divisor latch access. Set by user to enable access to the COMDIV0 and COMDIV1 registers. Cleared by user to disable access to COMDIV0 and COMDIV1 and enable access to COMRX, COMTX, and COMIEN0. Set break. Set by user to force transmit to 0. Cleared to operate in normal mode. Stick parity. Set by user to force parity to defined values. 1 if EPS = 1 and PEN = 1.
Data Sheet ADuC7060/ADuC7061 UART Control Register 1 Table 92. COMSTA0 MMR Bit Designations This 8-bit register controls the operation of the UART in conjunction with COMCON0. COMCON1 Register Name: COMCON1 Address: 0xFFFF0710 Default value: 0x00 Access: Read and write Bit 7 6 Name 5 THRE 4 BI 3 FE 2 PE 1 OE 0 DR TEMT Table 91. COMCON1 MMR Bit Designations Bit 7:5 4 Name LOOPBACK 3:2 1 RTS 0 DTR Description Reserved bits. Not used. Loopback.
ADuC7060/ADuC7061 UART Status Register 1 COMSTA1 Register Name: COMSTA1 Address: 0xFFFF0718 Default value: 0x00 Access: Read only Function: COMSTA1 is a modem status register. Data Sheet Table 94. COMIEN0 MMR Bit Designations Bit 7:4 3 Name 2 ELSI 1 ETBEI 0 ERBFI EDSSI Table 93. COMSTA1 MMR Bit Designations Bit 7:5 4 3:1 0 Name CTS DCTS Description Reserved. Not used. Clear to send. Reserved. Not used. Delta CTS. Set automatically if CTS changed state since COMSTA1 was last read.
Data Sheet ADuC7060/ADuC7061 Table 95. COMIID0 MMR Bit Designations Status Bits[2:1] 00 11 Bit 0 1 0 Priority 10 0 2 1 01 0 3 00 0 4 Definition No interrupt Receive line status interrupt Receive buffer full interrupt Transmit buffer empty interrupt Modem status interrupt Table 96.
ADuC7060/ADuC7061 Data Sheet I2C • Each ADuC706x incorporates an I2C peripheral that can be configured as a fully I2C-compatible I2C bus master device or as a fully I2C bus-compatible slave device. The two pins used for data transfer, SDA and SCL, are configured in a wire-AND’ed format that allows arbitration in a multimaster system. These pins require external pull-up resistors. Typical pull-up resistor values are between 4.7 kΩ and 10 kΩ.
Data Sheet ADuC7060/ADuC7061 SERIAL CLOCK GENERATION I2CID0[7:1] = Address Bits[6:0]. The I2C master in the system generates the serial clock for a transfer. The master channel can be configured to operate in fast mode (400 kHz) or standard mode (100 kHz). I2CID1[2:0] = Address Bits[9:7]. The bit rate is defined in the I2CDIV MMR as follows: f SERIAL CLOCK I2CID1[7:3] must be set to 11110b. Master Mode In master mode, the I2CADR0 register is programmed with the I2C address of the device.
ADuC7060/ADuC7061 Data Sheet Table 97. I2CMCON MMR Bit Designations Bit 15:9 8 Name I2CMCENI 7 I2CNACKENI 6 I2CALENI 5 I2CMTENI 4 I2CMRENI 3 I2CMSEN 2 I2CILEN 1 I2CBD 0 I2CMEN Description Reserved. These bits are reserved and should not be written to. I2C transmission complete interrupt enable bit. Set this bit to enable an interrupt on detecting a stop condition on the I2C bus. Clear this interrupt source. I2C no acknowledge (NACK) received interrupt enable bit.
Data Sheet ADuC7060/ADuC7061 I2C Master Status, I2CMSTA, Register Name: I2CMSTA Address: 0xFFFF0904 Default value: 0x0000 Access: Read only Function: This 16-bit MMR is the I2C status register in master mode. Table 98. I2CMSTA MMR Bit Designations Bit 15:11 10 Name 9 I2CMRxFO 8 I2CMTC 7 I2CMNA 6 I2CMBUSY 5 I2CAL 4 I2CMNA 3 I2CMRXQ 2 I2CMTXQ 1:0 I2CMTFSTA I2CBBUSY Description Reserved. These bits are reserved. I2C bus busy status bit.
ADuC7060/ADuC7061 Data Sheet I2C Master Receive, I2CMRX, Register I2C Master Current Read Count, I2CMCNT1, Register Name: I2CMRX Name: I2CMCNT1 Address: 0xFFFF0908 Address: 0xFFFF0914 Default value: 0x00 Default value: 0x00 Access: Read only Access: Read only Function: This 8-bit MMR is the I2C master receive register. Function: This 8-bit MMR holds the number of bytes received so far during a read sequence with a slave device.
Data Sheet ADuC7060/ADuC7061 I2C Address 1, I2CADR1, Register I2C Master Clock Control, I2CDIV, Register Name: I2CADR1 Name: I2CDIV Address: 0xFFFF091C Address: 0xFFFF0924 Default value: 0x00 Default value: 0x1F1F Access: Read and write Access: Read and write Function: This 8-bit MMR is used in 10-bit addressing mode only. This register contains the least significant byte of the address.
ADuC7060/ADuC7061 Data Sheet Table 104. I2CSCON MMR Bit Designations Bit 15:11 10 Name 9 I2CSRXENI 8 I2CSSENI 7 I2CNACKEN 6 I2CSSEN 5 I2CSETEN 4 I2CGCCLR 3 I2CHGCEN 2 I2CGCEN 1 ADR10EN 0 I2CSEN I2CSTXENI Description Reserved bits. Slave transmit interrupt enable bit. Set this bit to enable an interrupt after a slave transmits a byte. Clear this interrupt source. Slave receive interrupt enable bit. Set this bit to enable an interrupt after the slave receives data.
Data Sheet ADuC7060/ADuC7061 I2C Slave Status, I2CSSTA, Register Name: I2CSSTA Address: 0xFFFF092C Default value: 0x0000 Access: Read and write Function: This 16-bit MMR is the I2C status register in slave mode. Table 105. I2CSSTA MMR Bit Designations Bit 15 14 Name 13 I2CREPS 12:11 I2CID[1:0] 10 I2CSS 9:8 I2CGCID[1:0] 7 I2CGC 6 I2CSBUSY 5 I2CSNA 4 I2CSRxFO 3 I2CSRXQ I2CSTA Description Reserved bit.
ADuC7060/ADuC7061 Bit 2 Name I2CSTXQ 1 I2CSTFE 0 I2CETSTA Data Sheet Description I2C slave transmit request bit. This bit is set to 1 when the slave receives a matching address followed by a read. If the I2CSETEN bit in I2CSCON is =0, this bit goes high just after the negative edge of SCL during the read bit transmission. If the I2CSETEN bit in I2CSCON is =1, this bit goes high just after the positive edge of SCL during the read bit transmission.
Data Sheet ADuC7060/ADuC7061 I2C Common Registers I2C FIFO Status, I2CFSTA, Register Table 106. I2CFSTA MMR Bit Designations Bit 15:10 9 Name 0x0000 8 I2CFSTX Access: Read and write 7:6 I2CMRXSTA Function: This 16-bit MMR contains the status of the receive/transmit FIFOs in both master and slave modes. 5:4 I2CMTXSTA 3:2 I2CSRXSTA 1:0 I2CSTXSTA Name: I2CFSTA Address: 0xFFFF094C Default value: Rev. D | Page 95 of 108 I2CFMTX Description Reserved bits.
ADuC7060/ADuC7061 Data Sheet SERIAL PERIPHERAL INTERFACE The ADuC706x integrates a complete hardware serial peripheral interface (SPI) on chip. SPI is an industry standard, synchronous serial interface that allows eight bits of data to be synchronously transmitted and simultaneously received, that is, full duplex up to a maximum bit rate of 5.12 Mbps. In slave mode, the SPICON register must be configured with the phase and polarity of the expected input clock.
Data Sheet ADuC7060/ADuC7061 SPI REGISTERS The following MMR registers control the SPI interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON. SPI Status Register SPISTA Register Name: SPISTA Address: 0xFFFF0A00 Default value: 0x00000000 Access: Read only Function: This 32-bit MMR contains the status of the SPI interface in both master and slave modes. Table 107.
ADuC7060/ADuC7061 Data Sheet SPI Receive Register SPIRX Register Name: SPIRX Address: 0xFFFF0A04 Default value: 0x00 Access: Read only Function: This 8-bit MMR is the SPI receive register. Table 108. SPIDIV MMR Bit Designations Bit 7:6 5:0 Description Reserved.
Data Sheet ADuC7060/ADuC7061 Table 109. SPICON MMR Bit Designations Bit 15:14 Name SPIMDE 13 SPITFLH 12 SPIRFLH 11 SPICONT Description SPI IRQ mode bits. These bits are configured when transmit/receive interrupts occur in a transfer. [00] = transmit interrupt occurs when 1 byte has been transferred. Receive interrupt occurs when one or more bytes have been received into the FIFO. [01] = transmit interrupt occurs when 2 bytes have been transferred.
ADuC7060/ADuC7061 Bit 1 Name SPIMEN 0 SPIEN Data Sheet Description Master mode enable bit. Set by user to enable master mode. Cleared by user to enable slave mode. SPI enable bit. Set by user to enable the SPI. Cleared by user to disable the SPI. Rev.
Data Sheet ADuC7060/ADuC7061 GENERAL-PURPOSE I/O The ADuC706x features up to 16 general-purpose bidirectional input/output (GPIO) pins. In general, many of the GPIO pins have multiple functions that are configurable by user code. By default, the GPIO pins are configured in GPIO mode. All GPIO pins have an internal pull-up resistor with a drive capability of 1.6 mA. All I/O pins are 3.3 V tolerant, meaning that the GPIOs support an input voltage of 3.3 V.
ADuC7060/ADuC7061 Data Sheet Table 112. GPxCON MMR Bit Designations Bit 31:30 29:28 27:26 25:24 23:22 21:20 19:18 17:16 15:14 13:12 11:10 9:8 7:6 5:4 3:2 1:0 Description Reserved. Reserved. Reserved. Selects the function of the P0.6/RTS and P1.6/PWM pins. Reserved. Selects the function of the P0.5/CTS and P1.5/PWM3 pins. Reserved. Selects the function of the P0.4/IRQ0/PWM1 and P1.4/PWM2 pins. Reserved. Selects the function of the P0.3/MOSI/SDA and P1.3/TRIP pins. Reserved. Selects the function of the P0.
Data Sheet ADuC7060/ADuC7061 Table 120. GPxPAR MMR Bit Designations Table 122. GP0CON1 MMR Bit Designations Bit 31:15 23:16 Bit 7:2 15:8 7:0 Name GPL[7:0] GPDS[7:0] GPPD[7:0] Description Reserved. General I/O port pin functionality lock registers. GPL[7:0] = 0, normal operation. GPL[7:0] = 1, for each GPIO pin, if this bit is set, writing to the corresponding bit in GPxCON or GPxDAT register bit has no effect. Drive strength configuration. This bit is configurable.
ADuC7060/ADuC7061 Data Sheet HARDWARE DESIGN CONSIDERATIONS POWER SUPPLIES DIGITAL SUPPLY The ADuC706x operational power supply voltage range is 2.375 V to 2.625 V. Separate analog and digital power supply pins (AVDD and DVDD, respectively) allow AVDD to be kept relatively free of noisy digital signals often present on the system DVDD line. In this mode, the part can also operate with split supplies; that is, it can use different voltage levels for each supply.
Data Sheet ADuC7060/ADuC7061 OUTLINE DIMENSIONS 5.00 BSC SQ 0.60 MAX 0.60 MAX 32 1 25 24 0.50 BSC 3.65 3.50 SQ 3.35 EXPOSED PAD 17 8 16 0.50 0.40 0.30 TOP VIEW 1.00 0.85 0.80 0.80 MAX 0.65 TYP 12° MAX 0.25 MIN BOTTOM VIEW 3.50 REF 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.30 0.25 0.18 SEATING PLANE 9 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 30.
ADuC7060/ADuC7061 Data Sheet 0.75 0.60 0.45 9.20 9.00 SQ 8.80 1.60 MAX 37 48 36 1 PIN 1 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY SEATING PLANE (PINS DOWN) 25 12 13 VIEW A 0.50 BSC LEAD PITCH VIEW A 24 0.27 0.22 0.17 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC 051706-A 0.15 0.05 7.20 7.00 SQ 6.80 TOP VIEW 1.45 1.40 1.35 Figure 32.
Data Sheet ADuC7060/ADuC7061 NOTES Rev.
ADuC7060/ADuC7061 Data Sheet NOTES ©2009–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07079-0-4/12(D) Rev.