MicroConverter®, Small Package 12-Bit ADC with Embedded Flash MCU ADuC814 FEATURES APPLICATIONS Optical networking—laser power control Base station systems—power amplifier bias control Precision instruments, smart sensors Battery-powered systems, precision system monitors FUNCTIONAL BLOCK DIAGRAM ADuC814 AIN0 AIN MUX T/H 12-BIT ADC AIN5 ADC CONTROL LOGIC DAC CONTROL LOGIC DAC0 BUF DAC0 DAC1 BUF DAC1 TEMP MONITOR INTERNAL BAND GAP VREF VREF CREF BUF POWERON RESET PROG.
ADuC814 TABLE OF CONTENTS Specifications..................................................................................... 4 ADC Offset and Gain Calibration Overview ......................... 28 Absolute Maximum Ratings............................................................ 9 ADC Offset and Gain Calibration Coefficients ..................... 28 ESD Caution.................................................................................. 9 Calibrating the ADC ....................................
ADuC814 Serial Peripheral Interface..........................................................44 SBUF.........................................................................................53 MISO (Master In, Slave Out Data I/O Pin) .........................44 Mode 0: 8-Bit Shift Register Mode .......................................54 MOSI (Master Out, Slave In Pin)..........................................44 Mode 1: 8-Bit UART, Variable Baud Rate ............................
ADuC814 SPECIFICATIONS Table 1. AVDD = DVDD = 2.7 V to 3.3 V or 4.5 V to 5.5 V, VREF = 2.5 V internal reference, XTAL1/XTAL2 = 32.768 kHz crystal.
ADuC814 Parameter TEMPERATURE MONITOR9 Voltage Output at 25ºC Voltage TC Accuracy Accuracy DAC CHANNEL SPECIFICATIONS DC ACCURACY10 Resolution Relative Accuracy Differential Nonlinearity11 Offset Error Gain Error Gain Error Mismatch ANALOG OUTPUTS Voltage Range_0 Voltage Range_1 Output Impedance ISINK DAC AC Specifications Voltage Output Settling Time Digital-to-Analog Glitch Energy REFERENCE INPUT/OUTPUT REFERENCE OUTPUT Output Voltage (VREF) Accuracy Power Supply Rejection Reference Tempco Internal VREF P
ADuC814 Parameter SCLOCK and RESET Only14 (Schmitt-Triggered Inputs) VT+ VT– VT+ – VT– INPUT CURRENTS P1.2–P1.7, DLOAD SCLOCK15 RESET P1.0, P1.1, Port 315 (includes MISO, MOSI/SDATA and SS) INPUT CAPACITANCE CRYSTAL OSCILLATOR (XTAL1 AND XTAL2) Logic Inputs, XTAL1 Only VINL, Input Low Voltage VINH, Input High Voltage XTAL1 Input Capacitance XTAL2 Output Capacitance DIGITAL OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) Port 1.0 and Port 1.1 Port 1.0 and Port 1.
ADuC814 Parameter Oscillator Powered Down16 Wake-Up with INT0 Interrupt Wake-Up with SPI/I2C Interrupt Wake-Up with External RESET After External RESET in Normal Mode After WDT Reset in Normal Mode FLASH/EE MEMORY RELIABILITY CHARACTERISTICS17 Endurance18 Data Retention19 POWER REQUIREMENTS20, 21 Power Supply Voltages AVDD/DVDD – AGND VDD = 5 V VDD = 3 V Unit 150 150 150 3 3 400 400 400 3 3 ms typ ms typ ms typ ms typ ms typ 100,000 100 100,000 100 Cycles min Years min 2.7 3.
ADuC814 1 Temperature range –40ºC to +125ºC. ADC linearity is guaranteed when operating in nonpipelined mode, i.e., ADC conversion followed sequentially by a read of the ADC result. ADC linearity is also guaranteed during normal MicroConverter core operation. 3 ADC LSB size = VREF /212, i.e., for internal VREF = 2.5 V, 1 LSB = 610 µV, and for external VREF = 1 V, 1 LSB = 244 µV. 4 Offset and gain error and offset and gain error match are measured after factory calibration.
ADuC814 ABSOLUTE MAXIMUM RATINGS Table 2.
ADuC814 PIN CONFIGURATION AND FUNCTION DESCRIPTION DGND 1 28 DVDD DLOAD 2 27 XTAL2 P3.0/RxD 3 26 XTAL1 P3.1/TxD 4 25 SCLOCK P3.2/INT0 5 24 P3.7/SDATA/MOSI P3.3/INT1 6 P3.4/T0/CONVST 7 23 P3.6/MISO ADuC814 RESET 10 19 P1.5/ADC3 P1.2/ADC0 11 18 P1.4/ADC2 P1.3/ADC1 12 17 CREF AVDD 13 16 VREF AGND 14 15 AGND 02748-A-009 22 P3.5/T1/SS/EXTCLK TOP VIEW P1.0/T2 8 (Not to Scale) 21 P1.7/ADC5/DAC1 20 P1.6/ADC4/DAC0 P1.1/T2EX 9 Figure 2. Pin Configuration Table 3. Pin Descriptions Pin No.
ADuC814 Pin No. 17 18–21 Mnemonic CREF P1.4–P1.7 Type I I 18 19 20 I I I/O 22–24 P1.4/ADC2 P1.5/ADC3 P1.6/ADC4/ DAC0 P1.7/ ADC5/DAC1 P3.5–P3.7 22 P3.5/T1 22 P3.5/SS /EXTCLK I/O 23 24 P3.6/MISO P3.7/SDATA/ MOSI SCLOCK XTAL1 XTAL2 DVDD I/O I/O Function Decoupling Input for On-Chip Reference. Connect 0.1 µF between this pin and AGND. Port 1.4 to P1.7. These pins have no digital output drivers, i.e., they can only function as digital inputs, for which 0 must be written to the port bit.
ADuC814 TERMINOLOGY ADC SPECIFICATIONS DAC SPECIFICATIONS Integral Nonlinearity Relative Accuracy This is the maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point1/2 LSB below the first code transition and full scale, a point 1/2 LSB above the last code transition.
ADuC814 TYPICAL PERFORMANCE CURVES Figure 5 and Figure 6 show the variation in worst-case positive (WCP) INL and worst-case negative (WCN) INL versus external reference input voltage. 1.2 AVDD /DVDD = 5V 0.4 AVDD/DVDD = 5V fS = 152kHz 0.3 0.4 0.8 0.6 WCP–INL (LSBs) Figure 3 and Figure 4 show typical ADC integral nonlinearity (INL) errors from ADC Code 0 to Code 4095 at 5 V and 3 V supplies, respectively. The ADC is using its internal reference (2.5 V) and operating at a sampling rate of 152 kHz.
ADuC814 0.30 0.7 0.7 AVDD/DVDD = 3V fS = 152kHz 0.25 0.5 0.5 0.20 WCP–DNL (LSBs) LSBs 0.10 0.05 0 –0.50 0.3 0.3 0.1 0.1 –0.1 –0.1 WCN DNL –0.3 –0.3 –0.5 –0.5 WCN–DNL (LSBs) WCP DNL 0.15 –0.15 –0.25 0 511 1023 1535 2047 2559 ADC CODES 3071 3583 4095 –0.7 –0.7 02748-A-014 AVDD/DVDD = 5V fS = 152kHz –0.20 0.5 1.0 1.5 2.0 2.5 EXTERNAL REFERENCE (V) 3.0 02748-A-017 –0.10 Figure 10. Typical Worst-Case DNL Error vs. VREF, VDD = 3 V Figure 7.
ADuC814 Figure 15 and Figure 16 show typical dynamic performance versus external reference voltages. Again excellent ac performance can be observed in both plots with some roll-off being observed as VREF falls below 1 V. AVDD /DVDD = 5V fS = 152kHz 75 –75 SNR –80 70 20 –20 –40 SNR (dBs) AVDD/DVDD = 5V fS = 149.79kHz fIN = 9.910kHz SNR = 71.3dB THD = –88.0dB ENOB = 11.
ADuC814 ADuC814 ARCHITECTURE, MAIN FEATURES reference. On-chip digital peripherals include a watchdog timer, time interval counter, three timer/counters, and three serial I/O ports (SPI, UART, I2C). The ADuC814 is a fully integrated 247 kSPS 12-bit data acquisition system incorporating a high performance multichannel ADC, an 8-bit MCU, and program/data Flash/EE memory on a single chip.
ADuC814 MEMORY ORGANIZATION DATA MEMORY SPACE READ/WRITE The ADuC814 does not have Port 0 and Port 2 pins and therefore does not support external program or data memory interfaces. The device executes code from the internal 8-kByte Flash/EE program memory. This internal code space can be programmed via the UART serial port interface while the device is in-circuit. The program memory space of the ADuC814 is shown in Figure 18.
ADuC814 The SFR space is mapped to the upper 128 bytes of internal data memory space and is accessed by direct addressing only. It provides an interface between the CPU and all on-chip peripherals. A block diagram showing the programming model of the ADuC814 via the SFR area is shown in Figure 21. A complete SFR map is shown in Figure 22.
ADuC814 Power Control SFR The power control (PCON) register contains bits for power-saving options and general-purpose status flags as shown in Table 5. SFR Address Power-On Default Bit Addressable SMOD 87H 00H No SERIPD INT0PD --- GF1 Table 5. PCON SFR Bit Designations Bit No. 7 6 5 4 3 2 1 0 Name SMOD SERIPD INT0PD RSVD GF1 GF0 PD IDL Description Double UART Baud Rate. SPI Power-Down Interrupt Enable. INT0 Power-Down Interrupt Enable. Reserved. General-Purpose Flag Bit. General-Purpose Flag Bit.
ADuC814 SPECIAL FUNCTION REGISTERS Unoccupied locations in the SFR address space are not implemented, i.e., no register exists at this location. If an unoccupied location is read, an unspecified value is returned. SFR locations reserved for future use are shaded (RESERVED) and should not be accessed by the user software. All registers, except the program counter and the four generalpurpose register banks, reside in the SFR area.
ADuC814 ADC CIRCUIT INFORMATION GENERAL OVERVIEW ADC TRANSFER FUNCTION The ADC block incorporates a 4.05 msec, 6-channel, 12-bit resolution, single-supply ADC. This block provides the user with a multichannel multiplexer, track-and-hold amplifier, onchip reference, offset calibration features and ADC. All components in this block are easily configured via a 3-register SFR interface. The analog input range for the ADC is 0 V to VREF.
ADuC814 SFR INTERFACE TO ADC BLOCK The ADC operation is fully controlled via three SFRs: ADCCON1, ADCCON2, and ADCCON3. These three registers control the mode of operation. ADCCON1 (ADC CONTROL SFR 1) The ADCCON1 register controls conversion and acquisition times, hardware conversion modes, and power-down modes as detailed below. SFR Address SFR Power-on Default Bit Addressable MODE EFH 00H No EXT_REF CK1 CK0 AQ1 AQ0 T2C EXC Table 6. ADCCON1 SFR Bit Designations Bit No.
ADuC814 ADCCON2 (ADC CONTROL SFR 2) The ADCCON2 (byte addressable) register controls ADC channel selection and conversion modes as detailed below. SFR Address SFR Power-On Default Bit Addressable ADCI D8H 00H Yes ADCSPI CCONV SCOVC CS3 CS2 CS1 CS0 Table 7. ADCCON2 SFR Bit Designations Bit No. 7 Name ADCI 6 ADCSPI 5 CCONV 4 SCONV 3 2 1 0 CS3 CS2 CS1 CS0 Description ADC Interrupt Bit. ADCI is set at the end of a single ADC conversion cycle.
ADuC814 ADCCON3 (ADC CONTROL SFR 3) The ADCCON3 register controls the operation of various calibration modes as well as giving an indication of ADC busy status. SFR Address SFR Power-On Default BUSY F5H 00H GNCLD AVGS1 AVGS0 OFCLD MODCAL TYPECAL Table 8. ADCCON3 SFR Bit Designations Bit No. 7 Name BUSY 6 GNCLD 5 4 AVGS1 AVGS0 3 OFCLD 2 MODCAL 1 TYPECAL 0 SCAL Description ADC Busy Status Bit. BUSY is a read-only status bit that is set during a valid ADC conversion or calibration cycle.
ADuC814 DRIVING THE ADC ADuC814 VREF AGND DAC1 DAC0 TEMPERATURE MONITOR INTERNAL CHANNELS ADuC814 10Ω AIN0 0.1µF 02748-A-033 The ADC incorporates a successive approximation architecture (SAR) involving a charge-sampled input stage. Each ADC conversion is divided into two distinct phases as defined by the position of the switches in Figure 25.
ADuC814 Table 10. Some Single-Supply Op Amps Op Amp Model OP281/OP481 OP191/OP291/OP491 OP196/OP296/OP496 OP183/OP283 OP162/OP262/OP462 AD820/OP822/OP824 AD823 Characteristics Micropower I/O good up to VDD, low cost I/O to VDD, micropower, low cost High gain-bandwidth product High GBP, micropackage FET input, low cost FET input, high GBP If an external voltage reference is preferred, it should be connected to the VREF and CREF pins as shown in Figure 28.
ADuC814 Both the ADCCLK frequency and the acquisition time are used in determining the ADC conversion time. Two other parameters are also used in this calculation. To convert the acquired signal into its corresponding digital output word takes 15 ADCCLK periods (TCONV). When a conversion is initiated, the start of conversion signal is synchronized to the ADCCLK. This synchronization (TSYNC) can take from 0.5 to 1.5 ADCCLKs to occur.
ADuC814 CONVST SCLOCK MOSI ADCDATAH ADCDATAL ADCDATAH ADCDATAL ADCDATAH ADCDATAL 02748-A-037 BUSY Figure 30. High Speed Data Capture Logic Timing (Pipelined Mode) In this mode, the ADC to SPI data transfer occurs during the next ADC conversion. To avoid loss of an ADC result, the user must ensure that the ADC to SPI transfer rate is complete before the current ADC conversion ends.
ADuC814 gain coefficient compensates for a larger analog input signal range and scales down the ADC transfer function, effectively decreasing the slope of the transfer function. The maximum analog input signal range for which the gain coefficient can compensate is 1.035 × VREF, and the minimum input range is 0.965 × VREF, which equates to typically ±3.5% of the reference voltage.
ADuC814 NONVOLITILE FLASH/EE MEMORY FLASH/EE MEMORY OVERVIEW The ADuC814 incorporates Flash/EE memory technology onchip to provide the user with nonvolatile, in-circuit reprogrammable code and data memory space. Endurance quantifies the ability of the Flash/EE memory to be cycled through many program, read, and erase cycles.
ADuC814 5V USING FLASH/EE PROGRAM MEMORY VDD The Flash/EE program memory array can be programmed in one of two modes: serial downloading and parallel programming. P3 GND DATA ADuC814 As part of its factory boot code, the ADuC814 facilitates code download via the standard UART serial port. Serial download mode is automatically entered on power-up or during a hardware RESET operation if the external DLOAD pin is pulled high through an external resistor, as shown in Figure 34.
ADuC814 USING FLASH/EE DATA MEMORY The user Flash/EE data memory array consists of 640 bytes that are configured into 160 (00H to 9FH) 4-byte pages as shown in Figure 36. 9FH A block diagram of the SFR interface to the Flash/EE data memory array is shown in Figure 37.
ADuC814 FLASH/EE MEMORY TIMING The typical program/erase times for the Flash/EE data memory are Erase Full Array (640 bytes) 2 ms Erase Single Page (4 bytes) 2 ms Program Page (4 bytes) 250 µs Read Page (4 bytes) Within single instruction cycle shipped from the factory pre-erased, i.e., byte locations set to FFH, it is nonetheless good programming practice to include an ERASE-ALL routine as part of any configuration/setup code running on the ADuC814.
ADuC814 USER INTERFACE TO OTHER ON-CHIP ADuC814 PERIPHERALS This section gives a brief overview of the various peripherals also available on-chip. A summary of the SFRs used to control and configure these peripherals is also given. DACS The ADuC814 incorporates two 12-bit, voltage output DACs on-chip. Each DAC has a rail-to-rail voltage output buffer capable of driving 10 kΩ/100 pF. They have two selectable ranges, 0 V to VREF (an external or the internal band gap 2.
ADuC814 DACxH/L Function SFR Address DAC0 and DAC1 Data Registers DAC Data Registers, written by the user to update the DAC outputs. DAC0L (DAC0 data low byte) –> F9H DAC0H (DAC0 data high byte) –> FAH; DAC1L (DAC1 data low byte) –> FBH DAC1H (DAC1 data high byte) –> FCH 00H –> Both DAC0 and DAC1 data registers. No –> Both DAC0 and DAC1 data registers.
ADuC814 5 For larger loads, the current drive capability may not be sufficient. To increase the source and sink current capability of the DACs, an external buffer should be added, as shown in Figure 42. DAC LOADED WITH 0FFFH 3 DAC0 ADuC814 2 DAC1 02748-A-046 1 DAC LOADED WITH 0000H 0 0 5 10 SOURCE/SINK CURRENT (mA) 4 DAC LOADED WITH 0FFFH OUTPUT VOLTAGE (V) Figure 42. Buffering the DAC Outputs 15 Figure 40.
ADuC814 ON-CHIP PLL The ADuC814 is intended for use with a 32.768 kHz watch crystal. An on-board PLL locks onto a multiple (512) of this 32.768kHz frequency to provide a stable 16.777216 MHz clock for the system. The core can operate at this frequency or at binary submultiples of it to allow power saving in cases where maximum core performance is not required. The default core clock is the PLL clock divided by 8 (2CD = 23) or 2.097152 MHz. The PLL is controlled via the PLLCON special function register.
ADuC814 TIME INTERVAL COUNTER (TIC) Six SFRs are associated with the time interval counter, TIMECON being its control register. Depending on the configuration of the IT0 and IT1 bits in TIMECON, the selected time counter register overflow clocks the interval counter. When this counter is equal to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON.2) is set and generates an interrupt if enabled. (See IEIP2 SFR description under the Interrupt System section.
ADuC814 TIMECON SFR Address Power-On Default Bit Addressable --- TIC CONTROL REGISTER A1H 00H No TFH ITS1 ITS0 STI TII TIEN TCEN Table 14. TIMECON SFR Bit Designations Bit No. 7 6 Name --TFH Description Reserved. Twenty-Four Hour Select Bit. Set by the user to enable the HOUR counter to count from 0 to 23. Cleared by the user to enable the HOUR counter to count from 0 to 255. The time interval counter continues to count after a reset when in hours/min/sec mode.
ADuC814 INTVAL Function SFR Address Power-On Default Bit Addressable Valid Value HTHSEC Function SFR Address Power-On Default Bit Addressable Valid Value SEC Function SFR Address Power-On Default Bit Addressable Valid Value MIN Function SFR Address Power-On Default Bit Addressable Valid Value HOUR Function SFR Address Power-On Default Bit Addressable Valid Value User Time Interval Select Register User code writes the required time interval to this register.
ADuC814 WATCHDOG TIMER The purpose of the watchdog timer is to generate a device reset or interrupt within a reasonable amount of time if the ADuC814 enters an erroneous state, possibly due to a programming error, electrical noise, or RFI. The watchdog function can be disabled by clearing the WDE (watchdog enable) bit in the watchdog control (WDCON) SFR.
ADuC814 POWER SUPPLY MONITOR As its name suggests, the power supply monitor, once enabled, monitors the supply (DVDD) on the ADuC814. It indicates when any of the supply pins drop below one of four user-selectable voltage trip points from 2.63 V to 4.63 V. For correct operation of the power supply monitor function, DVDD must be equal to or greater than 2.7 V. Monitor function is controlled via the PSMCON SFR. If enabled via the IEIP2 SFR, the monitor interrupts the core using the PSMI bit in the PSMCON SFR.
ADuC814 ADuC814 CONFIGURATION REGISTER (CFG814) The ADuC814 is housed in a 28-lead TSSOP package. To maintain as much functional compatibility with other MicroConverter products, some pins share multiple I/O functionality. Switching between these functions is controlled via the ADuC814 configuration SFR, CFG814, located at SFR address 9CH. A summary of these functions is described and a detailed bit designation for the CFG814 SFR is given in Table 17.
ADuC814 SERIAL PERIPHERAL INTERFACE The ADuC814 integrates a complete hardware serial peripheral interface (SPI) on-chip. SPI is an industry-standard synchronous serial interface that allows eight bits of data to be synchronously transmitted and received simultaneously, i.e., full duplex. Note that the SPI pins MISO and MOSI are multiplexed with digital outputs P3.6 and P3.7. These pins are controlled via the CFG814.
ADuC814 Bit No. 2 Name CPHA1 1 0 SPR1 SPR0 Description Clock Phase Select Bit. Set by the user if the leading SCLOCK edge is to transmit data. Cleared by the user if the trailing SCLOCK edge is to transmit data. SPI Bit Rate Select Bits. These bits select the SCLOCK rate (bit rate) in master mode as follows: SPR1 SPR0 Selected Bit Rate 0 0 fCORE/2 0 1 fCORE/4 1 0 fCORE/8 1 1 fcore/16 In SPI slave mode,where SPIM = 0, the logic level on the external SS pin (Pin 22), can be read via the SPR0 bit.
ADuC814 I2C COMPATIBLE INTERFACE The ADuC814 supports a 2-wire serial interface mode that is I2C compatible. The I2C compatible interface shares its pins with the on-chip SPI interface, and therefore the user can enable only one interface or the other at any given time (see the SPE bit in SPICON SFR, Table 18). Application Note uC001 describes the operation of this interface as implemented, and is available on the MicroConverter website at www.analog.com/microconverter.
ADuC814 8051 COMPATIBLE ON-CHIP PERIPHERALS This section gives a brief overview of the various secondary peripheral circuits that are available to the user on-chip. These functions are fully 8051 compatible and are controlled via standard 8051 SFR bit definitions. Parallel I/O Ports 1 and 3 The ADuC814 has two input/output ports. In addition to performing general-purpose I/O, some ports are multiplexed with an alternate function for the peripheral features on the device.
ADuC814 TIMERS/COUNTERS The ADuC814 has three 16-bit timer/counters: Timer 0, Timer 1, and Timer 2. The timer/counter hardware has been included on-chip to relieve the processor core of the overhead inherent in implementing timer/counter functionality in software. Each timer/counter consists of two 8-bit registers, THx and TLx (x = 0, 1 and 2). All three can be configured to operate either as timers or event counters. In timer function, the TLx register is incremented every machine cycle.
ADuC814 TCON SFR Address Power-On Default Bit Addressable TF1 1 Timer/Counter 0 and 1 Control Register 88H 00H Yes TR1 TF0 TR0 IE11 IT11 IE0 IT01 These bits are not used in the control of Timer/Counter 0 and 1, but are used instead in the control and monitoring of the external INT0 and INT1 interrupt pins. Table 23. TCON SFR Bit Designations Bit No. 7 Name TF1 6 TR1 5 TF0 4 TR0 3 IE1 2 IT1 1 IE0 0 IT0 Description Timer 1 Overflow Flag.
ADuC814 TIMER/COUNTER 0 AND 1 OPERATING MODES Mode 2 (8-Bit Timer/Counter with Autoreload) The following paragraphs describe the operating modes for Timer/Counters 0 and 1. Unless otherwise noted, it should be assumed that these modes of operation are the same for both Timer 0 and Timer 1. Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload, as shown in Figure 47.
ADuC814 T2CON SFR Address Power-On Default Bit Addressable TF2 Timer/Counter 2 Control Register C8H 00H Yes EXF2 RCLK TCLK EXEN2 TR2 CNT2 CAP2 Table 24. T2CON SFR Bit Designations Bit No. 7 Name TF2 6 EXF2 5 RCLK 4 TCLK 3 EXEN2 2 TR2 1 CNT2 0 CAP2 Description Timer 2 Overflow Flag. Set by hardware on a Timer 2 overflow. TF2 is not set when either RCLK or TCLK = 1. Cleared by the user software. Timer 2 External Flag.
ADuC814 TIMER/COUNTER 2 OPERATING MODES 16-Bit Capture Mode This section describes the operating modes for Timer/Counter 2. The operating modes are selected by bits in the T2CON SFR as shown in Table 27. In the capture mode, there are again two options that are selected by bit EXEN2 in T2CON. If EXEN2 = 0, then Timer 2 is a 16-bit timer or counter which, upon overflowing, sets bit TF2, the Timer 2 overflow bit, which can be used to generate an interrupt.
ADuC814 UART SERIAL INTERFACE The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can begin receiving a second byte before a previously received byte has been read from the receive register. However, if the first byte still has not been read by the time reception of the second byte is complete, the first byte is lost. The physical interface to the serial data network is via Pins RxD (P3.0) and TxD (P3.
ADuC814 Mode 0: 8-Bit Shift Register Mode Reception is initiated when a 1-to-0 transition is detected on RxD. Assuming a valid start bit was detected, character reception continues. The start bit is skipped and the eight data bits are clocked into the serial port shift register. When all eight bits have been clocked in, the following events occur: Mode 0 is selected by clearing both the SM0 and SM1 bits in the SFR SCON. Serial data enters and exits through RxD. TxD outputs the shift clock.
ADuC814 Mode 2: 9-Bit UART with Fixed Baud Rate Mode 0 Baud Rate Generation Mode 2 is selected by setting SM0 and clearing SM1. In this mode, the UART operates in 9-bit mode with a fixed baud rate. The baud rate is fixed at Core_Clk/64 by default, although by setting the SMOD bit in PCON, the frequency can be doubled to Core_Clk/32. Eleven bits are transmitted or received, a start bit (Bit 0), eight data bits, a programmable ninth bit, and a stop bit (Bit 1).
ADuC814 Timer 2 Generated Baud Rates Baud rates can also be generated using Timer 2. Using Timer 2 is similar to using Timer 1 in that the timer must overflow 16 times before a bit is transmitted/received. Because Timer 2 has a 16-bit autoreload mode, a wide range of baud rates is possible using Timer 2.
ADuC814 INTERRUPT SYSTEM The ADuC814 provides a total of twelve interrupt sources with two priority levels. The control and configuration of the interrupt system is carried out through three interrupt-related SFRs. IE IP IEIP2 Interrupt Enable Register Interrupt Priority Register Secondary Interrupt Enable and Priority Register IE SFR Address Power-On Default Bit Addressable Interrupt Enable Register A8H 00H Yes EA EADC ET2 ES ET1 Table 29. IE SFR Bit Designations Bit No.
ADuC814 IP SFR Address Power-On Default Bit Addressable --- Interrupt Priority Register B8H 00H Yes PADC PT2 PS PT1 PX1 PT0 PX0 EPSM ESI Table 30. IP SFR Bit Designations Bit No. 7 6 Name --PADC 5 PT2 4 PS 3 PT1 2 PX1 1 PT0 0 PX0 Description Reserved. ADC Interrupt Priority. Written to by user to set interrupt priority level (1 = High; 0 = Low). Timer 2 Interrupt Priority. Written to by the user to set interrupt priority level (1 = High; 0 = Low). UART Serial Port Interrupt Priority.
ADuC814 Interrupt Priority Interrupt Vectors The interrupt enable registers are written by the user to enable individual interrupt sources, while the interrupt priority registers allow the user to select one of two priority levels for each interrupt. An interrupt of a high priority may interrupt the service routine of a low priority interrupt, and if two interrupts of different priority occur at the same time, the higher level interrupt is serviced first.
ADuC814 ADuC814 HARDWARE DESIGN CONSIDERATIONS DIGITAL SUPPLY This section outlines some key hardware design considerations for integrating the ADuC814 into any hardware system. ANALOG SUPPLY 10µF + – 10µF + – CLOCK OSCILLATOR ADuC814 AVDD DVDD 0.1µF 0.1µF AGND DGND 02748-A-061 As described earlier, the core clock frequency for the ADuC814 is generated from an on-chip PLL that locks onto a multiple (512 times) of 32.768 kHz. The latter is generated from an internal clock oscillator.
ADuC814 Setting the idle and power-down mode bits, PCON.0 and PCON.1, respectively, in the PCON SFR described in Table 5, allows the chip to be switched from normal mode to idle mode, and also to full power-down mode. In idle mode, the oscillator continues to run, but the core clock generated from the PLL is halted. The on-chip peripherals continue to receive the clock and remain functional.
ADuC814 OTHER HARDWARE CONSIDERATIONS a. PLACE ANALOG COMPONENTS HERE To facilitate in-circuit programming, in-circuit debug, and emulation options, users should implement some simple connection points in their hardware. A typical ADuC814 connection diagram is shown in Figure 59. PLACE DIGITAL COMPONENTS HERE AGND DGND In-Circuit Serial Download Access PLACE ANALOG COMPONENTS HERE PLACE DIGITAL COMPONENTS HERE AGND c.
ADuC814 DVDD 1kΩ 2-PIN HEADER FOR EMULATION ACCESS (NORMALLY OPEN) DVDD DOWN LOAD/DEBUG ENABLE JUMPER (NORMALLY OPEN) 0.1µF DVDD 28 1 DGND 2 DLOAD XTAL2 27 3 RXD XTAL1 26 4 TXD 25 23 6 ADuC814 7 DAC0 20 9 DVDD 10Ω 10nF AVDD 22 DAC1 21 8 10 RESET 11 ADC0 DAC0 OUTPUT 19 18 CREF 17 12 13 AVDD 14 AGND DAC1 OUTPUT 0.1µF VREF 16 0.
ADuC814 TIMING SPECIFICATIONS1,2,3 Table 34. Clock Input (External Clock Driven XTAL1) AVDD = 2.7 V to 3.3 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.3 V or 4.75 V to 5.25 V; all specifications TMIN to TMAX, unless otherwise noted Parameter tCK tCKL tCKH tCKR tCKF 1/tCORE tCORE tCYC 32.768 kHz External Crystal Typ Max 30.52 15.16 15.16 20 20 16.78 0.476 5.7 91.
ADuC814 Table 35. UART Timing (Shift Register Mode) 16.78 MHz Core_Clk Min Typ Max 715 463 252 0 22 Serial Port Clock Cycle Time Output Data Setup to Clock Input Data Setup to Clock Input Data Hold after Clock Output Data Hold after Clock Min 10 tCORE 2 tCORE 0 2 tCORE Variable Core_Clk Typ 12 tCORE –133 +133 Max –117 tXLXL TxD (OUTPUT CLOCK) SET RI OR SET TI tQVXH tXHQX RxD (OUTPUT DATA) LSB BIT 1 BIT 6 tDVXH RxD (INPUT DATA) LSB tXHDX BIT 1 BIT 6 Figure 62.
ADuC814 Table 36. SPI Master Mode Timing (CPHA = 1) Parameter tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF Typ 630 630 Max 50 100 100 10 10 10 10 25 25 25 25 Characterized under the following conditions: a. Core clock divider bits CD2, CD1, and CD0 in PLLCON SFR set to 0, 1, and 1, respectively, i.e., core clock frequency = 2.09 MHz. b. SPI bit-rate selection bits SPR1 and SPR0 bits in SPICON SFR set to 0 and 0, respectively.
ADuC814 Table 37. SPI Master Mode Timing (CPHA = 0) Parameter tSL tSH tDAV tDOSU tDSU tDHD tDF tDR tSR tSF Min SCLOCK Low Pulse Width1 SCLOCK High Pulse Width1 Data Output Valid after SCLOCK Edge Data Output Setup before SCLOCK Edge Data Input Setup Time before SCLOCK Edge Data Input Hold Time after SCLOCK Edge Data Output Fall Time Data Output Rise Time SCLOCK Rise Time SCLOCK Fall Time Typ 630 630 Max 50 150 100 100 10 10 10 10 25 25 25 25 1 Characterized under the following conditions: a.
ADuC814 Table 38.
ADuC814 Table 39.
ADuC814 OUTLINE DIMENSIONS 9.80 9.70 9.60 28 15 4.50 4.40 4.30 6.40 BSC 1 14 PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX SEATING PLANE 0.20 0.09 8° 0° 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153AE Figure 67. 28-Lead Thin Shrink Small Outline Package (TSSOP) (RU-28) Dimensions shown in mm Rev.
ADuC814 ORDERING GUIDE Model ADuC814ARU ADuC814ARU-REEL ADuC814ARU-REEL7 ADuC814BRU ADuC814BRU-REEL ADuC814BRU-REEL7 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C QuickStart Development System Model EVAL-ADUC814QS EVAL-ADUC814QSP1 Package Description Thin Shrink Small Outline (TSSOP) Thin Shrink Small Outline (TSSOP) Thin Shrink Small Outline (TSSOP) Thin Shrink Small Outline (TSSOP) Thin Shrink Small Outline (TSSOP) Thin Shrink Small Ou
ADuC814 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02748-0-12/03(A) Rev.