a MicroConverter ®, Dual 16-Bit/24-Bit - ADCs with Embedded 62 kB Flash MCU ADuC834 FEATURES High Resolution - ADCs 2 Independent ADCs (16-Bit and 24-Bit Resolution) 24-Bit No Missing Codes, Primary ADC 21-Bit rms (18.5-Bit p-p) Effective Resolution @ 20 Hz Offset Drift 10 nV/ C, Gain Drift 0.
ADuC834 TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 9 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . .
SPECIFICATIONS1 (AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) = 2.5 V, REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal; all specifications TMIN, to TMAX unless otherwise noted.
ADuC834 SPECIFICATIONS (continued) Parameter INTERNAL REFERENCE ADC Reference Reference Voltage Power Supply Rejection Reference Tempco DAC Reference Reference Voltage Power Supply Rejection Reference Tempco ADuC834 Test Conditions/Comments Unit 1.25 ± 1% 45 100 Initial Tolerance @ 25°C, VDD = 5 V V min/max dBs typ ppm/°C typ 2.
ADuC834 Parameter ADuC834 TRANSDUCER BURNOUT CURRENT SOURCES AIN+ Current –100 AIN– Current +100 Initial Tolerance @ 25°C Drift ± 10 0.
ADuC834 SPECIFICATIONS (continued) Parameter ADuC834 Test Conditions/Comments Unit VOL, Output Low Voltage14 2.4 2.4 0.4 V min V min V max Floating State Leakage Current2 Floating State Output Capacitance 0.4 0.4 ± 10 5 VDD = 5 V, ISOURCE = 80 A VDD = 3 V, ISOURCE = 20 A ISINK = 8 mA, SCLOCK, MOSI/SDATA ISINK = 10 mA, P1.0 and P1.1 ISINK = 1.6 mA, All Other Outputs 2.63 4.63 ± 3.0 ± 4.0 2.63 4.63 ± 3.0 ± 4.
ADuC834 Parameter POWER REQUIREMENTS Power Supply Voltages AVDD, 3 V Nominal Operation AVDD, 5 V Nominal Operation DVDD, 3 V Nominal Operation DVDD, 5 V Nominal Operation 5 V POWER CONSUMPTION Power Supply Currents Normal Mode18, 19 DVDD Current DVDD Current AVDD Current Typical Additional Power Supply Currents (AIDD and DIDD) PSM Peripheral Primary ADC Auxiliary ADC DAC Dual Current Sources 3 V POWER CONSUMPTION Power Supply Currents Normal Mode18, 19 DVDD Current DVDD Current AVDD Current ADuC834 Test C
ADuC834 NOTES 1 Temperature Range for ADuC834BS (MQFP package) is –40°C to +125°C. Temperature Range for ADuC834BCP (CSP package) is –40°C to +85°C. 2 These numbers are not production tested but are guaranteed by design and/or characterization data on production release. 3 System Zero-Scale Calibration can remove this error. 4 The primary ADC is factory calibrated at 25°C with AVDD = DVDD = 5 V yielding this full-scale error of 10 V.
ADuC834 ABSOLUTE MAXIMUM RATINGS1 PIN CONFIGURATION 52-Lead MQFP (TA = 25°C, unless otherwise noted.) AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V AVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V AGND to DGND2 . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V AVDD to DVDD . . . . . . . . . . . . . .
37 38 39 ADuC834 BUF AIN MUX ADC CONTROL AND CALIBRATION PRIMARY ADC 24-BIT - ADC AIN1 AIN2 DAC CONTROL PGA AIN MUX AIN4 AIN5 TEMP SENSOR BAND GAP REFERENCE REFIN ADC CONTROL AND CALIBRATION 19 MCU CORE PLL WITH PROG.
ADuC834 PIN FUNCTION DESCRIPTIONS (continued) Pin No. Pin No. 52-Lead 56-Lead MQFP CSP Mnemonic 3–4, 9–12 2–3, 11–14 P1.2–P1.7 Type* Description I P1.2/DAC/IEXC1 I/O P1.3/AIN5/IEXC2 P1.4/AIN1 P1.5/AIN2 P1.6/AIN3 P1.7/AIN4/DAC I/O I I I I/O Port 1.2 to Port 1.7 have no digital output driver; they can function as a digital input for which ‘0’ must be written to the port bit. As a digital input, these pins must be driven high or low externally.
ADuC834 PIN FUNCTION DESCRIPTIONS (continued) Pin No. Pin No. 52-Lead 56-Lead MQFP CSP Mnemonic Type* Description 28–31 36–39 30–33 39–42 P2.0–P2.7 (A8–A15) (A16–A23) I/O Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled externally low will source current because of the internal pull-up resistors.
ADuC834 16 bytes (128 bits), locations 20H through 2FH above the register banks, form a block of directly addressable bit locations at bit addresses 00H through 7FH. The stack can be located anywhere in the internal memory address space, and the stack depth can be expanded up to 2048 bytes.
ADuC834 When accessing the internal XRAM, the P0 and P2 port pins, as well as the RD and WR strobes, will not be output as per a standard 8051 MOVX instruction. This allows the user to use these port pins as standard I/O. SPECIAL FUNCTION REGISTERS (SFRS) The upper 1792 bytes of the internal XRAM can be configured to be used as an extended 11-bit stack pointer. By default, the stack will operate exactly like an 8052 in that it will roll over from FFH to 00H in the general-purpose RAM.
ADuC834 Stack Pointer (SP and SPH) Table II. PCON SFR Bit Designations The SP SFR is the stack pointer and is used to hold an internal RAM address that is called the ‘top of the stack.’ The SP Register is incremented before data is stored during PUSH and CALL executions. While the Stack may reside anywhere in on-chip RAM, the SP Register is initialized to 07H after a reset. This causes the stack to begin at location 08H. As mentioned earlier, the ADuC834 offers an extended 11-bit stack pointer.
ADuC834 implemented; i.e., no register exists at this location. If an unoccupied location is read, an unspecified value is returned. SFR locations that are reserved for future use are shaded (RESERVED) and should not be accessed by user software. COMPLETE SFR MAP Figure 6 shows a full SFR memory map and the SFR contents after RESET. NOT USED indicates unoccupied SFR locations.
ADuC834 ADC SFR INTERFACE Both ADCs are controlled and configured via a number of SFRs that are mentioned here and described in more detail in the following pages. ADCSTAT ADC Status Register. Holds general status of the primary and auxiliary ADCs. ADC0L/M/H Primary ADC 24-bit conversion result is held in these three 8-bit registers. ADCMODE ADC Mode Register. Controls general modes of operation for primary and auxiliary ADCs.
ADuC834 ADCMODE (ADC Mode Register) Used to control the operational mode of both ADCs. SFR Address Power-On Default Value Bit Addressable D1H 00H No Table V. ADCMODE SFR Bit Designations Bit Name Description 7 ––– Reserved for Future Use 6 ––– Reserved for Future Use 5 ADC0EN Primary ADC Enable. Set by the user to enable the primary ADC and place it in the mode selected in MD2–MD0 below. Cleared by the user to place the primary ADC in power-down mode. 4 ADC1EN Auxiliary ADC Enable.
ADuC834 ADC0CON (Primary ADC Control Register) and ADC1CON (Auxiliary ADC Control Register) The ADC0CON and ADC1CON SFRs are used to configure the primary and auxiliary ADC for reference and channel selection, unipolar or bipolar coding and, in the case of the primary ADC, for range (the auxiliary ADC operates on a fixed input range of ± VREF).
ADuC834 ADC0H/ADC0M/ADC0L (Primary ADC Conversion Result Registers) These three 8-bit registers hold the 24-bit conversion result from the primary ADC. SFR Address Power-On Default Value Bit Addressable ADC0H ADC0M ADC0L 00H No High Data Byte DBH Middle Data Byte DAH Low Data Byte D9H ADC0H, ADC0M, ADC0L ADC0H, ADC0M, ADC0L ADC1H/ADC1L (Auxiliary ADC Conversion Result Registers) These two 8-bit registers hold the 16-bit conversion result from the auxiliary ADC.
ADuC834 SF (Sinc Filter Register) The number in this register sets the decimation factor and thus the output update rate for the primary and auxiliary ADCs. This SFR cannot be written by user software while either ADC is active. The update rate applies to both primary and auxiliary ADCs and is calculated as follows: f ADC = Where: 1 1 × × f MOD 3 8 × SF value for the SF Register is 45H, resulting in a default ADC update rate of just under 20 Hz.
ADuC834 selected via the Sinc Filter (SF) SFR. It is important to note that the peak-to-peak resolution figures represent the resolution for which there will be no code flicker within a six-sigma limit. The QuickStart Development system PC software comes complete with an ADC noise evaluation tool. This tool can be easily used with the evaluation board to see these figures from silicon.
ADuC834 PRIMARY AND AUXILIARY ADC CIRCUIT DESCRIPTION Overview The ADuC834 incorporates two independent - ADCs (primary and auxiliary) with on-chip digital filtering intended for the measurement of wide dynamic range, low frequency signals such as those in weigh-scale, strain gage, pressure transducer, or temperature measurement applications. Primary ADC This ADC is intended to convert the primary sensor input.
ADuC834 Auxiliary ADC The auxiliary ADC is intended to convert supplementary inputs such as those from a cold junction diode or thermistor. This ADC is not buffered and has a fixed input range of 0 V to 2.5 V (assuming an external 2.5 V reference). The single-ended inputs can be driven from AIN3, AIN4, or AIN5 Pins, or directly from the on-chip temperature sensor voltage. A block diagram of the auxiliary ADC is shown in Figure 8.
ADuC834 19.372 Primary and Auxiliary ADC Inputs The output of the primary ADC multiplexer feeds into a high impedance input stage of the buffer amplifier. As a result, the primary ADC inputs can handle significant source impedances and are tailored for direct connection to external resistive-type sensors like strain gages or Resistance Temperature Detectors (RTDs). ADC INPUT VOLTAGE – mV 19.371 The auxiliary ADC, however, is unbuffered, resulting in higher analog input current on the auxiliary ADC.
ADuC834 If the voltage measured is 0 V, it indicates that the transducer has short circuited. For normal operation, these burnout currents are turned off by writing a 0 to the BO bit in the ICON SFR. The current sources work over the normal absolute input voltage range specifications. Reference Input The ADuC834’s reference inputs, REFIN(+) and REFIN(–), provide a differential reference input capability. The commonmode range for these differential inputs is from AGND to AVDD.
ADuC834 The response of the filter, however, will change with SF word as can be seen in Figure 12, which shows >90 dB NMR at 50 Hz and >70 dB NMR at 60 Hz when SF = 255 dec. 0 –10 –20 –30 –40 GAIN – dB In operation, the analog signal sample is fed to the difference amplifier along with the output of the feedback DAC. The difference between these two signals is integrated and fed to the comparator.
ADuC834 ADC Chopping input voltages provided to the input of the modulator during calibration. The result of the zero-scale calibration conversion is stored in the Offset Calibration Registers for the appropriate ADC. The result of the full-scale calibration conversion is stored in the Gain Calibration Registers for the appropriate ADC. With these readings, the calibration logic can calculate the offset and the gain slope for the input-to-output transfer function of the converter.
ADuC834 Like EEPROM, Flash memory can be programmed in-system at a byte level, although it must first be erased; the erase being performed in page blocks. Thus, Flash memory is often and more correctly referred to as Flash/EE memory. EPROM TECHNOLOGY As indicated in the specification pages of this data sheet, the ADuC834 Flash/EE memory endurance qualification has been carried out in accordance with JEDEC Specification A117 over the industrial temperature range of –40°C, +25°C, +85°C, and +125°C.
ADuC834 Flash/EE Program Memory (2) Parallel Programming The ADuC834 contains a 64 Kbyte array of Flash/EE program memory. The lower 62 Kbytes of this program memory is available to the user, and can be used for program storage or indeed as additional NV data memory. The parallel programming mode is fully compatible with conventional third party Flash or EEPROM device programmers. A block diagram of the external pin configuration required to support parallel programming is shown in Figure 18.
ADuC834 Alternatively ULOAD Mode can be used to save data to the 56 Kbytes of Flash/EE memory. This can be extremely useful in datalogging applications where the ADuC834 can provide up to 60 Kbytes of NV data memory on-chip (4 Kbytes of dedicated Flash/EE data memory also exist). The upper 6 Kbytes of the 62 Kbytes of Flash/EE program memory is only programmable via serial download or parallel programming. This means that this space appears as read only to user code.
3FFH BYTE 1 (0FFCH) BYTE 2 (0FFDH) BYTE 3 (0FFEH) BYTE 4 (0FFFH) 3FEH BYTE 1 (0FF8H) BYTE 2 (0FF9H) BYTE 3 (0FFAH) BYTE 4 (0FFBH) 03H BYTE 1 (000CH) BYTE 2 (000DH) BYTE 3 (000EH) BYTE 4 (000FH) 02H BYTE 1 (0008H) BYTE 2 (0009H) BYTE 3 (000AH) BYTE 4 (000BH) 01H BYTE 1 (0004H) BYTE 2 (0005H) BYTE 3 (0006H) BYTE 4 (0007H) BYTE 1 (0000H) BYTE 2 (0001H) BYTE 3 (0002H) BYTE 4 (0003H) EDATA3 SFR EDATA4 SFR PAGE ADDRESS (EADRH/L) The 4 Kbytes of Flash/EE data memory is configured as
ADuC834 Programming the Flash/EE Data Memory A user wishes to program F3H into the second byte on Page 03H of the Flash/EE data memory space while preserving the other three bytes already in this page. A typical program of the Flash/EE data array will involve: 1. setting EADRH/L with the page address 2. writing the data to be programmed to the EDATA1–4 3.
ADuC834 DAC The ADuC834 incorporates a 12-bit, voltage output DAC on-chip. It has a rail-to-rail voltage output buffer capable of driving 10 kΩ/100 pF. It has two selectable ranges, 0 V to VREF (the internal bandgap 2.5 V reference) and 0 V to AVDD. It can operate in 12-bit or 8-bit mode. The DAC has a control register, DACCON, and two data registers, DACH/L. The DAC output can be programmed to appear at Pin 3 or Pin 12.
ADuC834 Note that Figure 22 represents a transfer function in 0-to-VDD mode only. In 0-to-VREF mode (with VREF < VDD), the lower nonlinearity would be similar, but the upper portion of the transfer function would follow the “ideal” line right to the end, showing no signs of endpoint linearity errors. 4 OUTPUT VOLTAGE – V DAC LOADED WITH 0FFF HEX VDD VDD–50mV VDD–100mV 3 1 DAC LOADED WITH 0000 HEX 0 50mV 0mV FFF Hex 000 Hex Figure 22.
ADuC834 PULSEWIDTH MODULATOR (PWM) The PWM on the ADuC834 is a highly flexible PWM offering programmable resolution and input clock, and can be configured for any one of six different modes of operation. Two of these modes allow the PWM to be configured as a - DAC with up to 16 bits of resolution. A block diagram of the PWM is shown in Figure 26. 12.583MHz PWMCLK 32.768kHz CLOCK SELECT PROGRAMMABLE DIVIDER 32.768kHz/15 16-BIT PWM COUNTER P1.
ADuC834 PWM1L PWM MODES OF OPERATION Mode 0: PWM Disabled PWM COUNTER The PWM is disabled, allowing P1.0 and P1.1 be used as normal. PWM0H PWM0L Mode 1: Single-Variable Resolution PWM In Mode 1, both the pulse length and the cycle time (period) are programmable in user code, allowing the resolution of the PWM to be variable. PWM1H/L sets the period of the output waveform. Reducing PWM1H/L reduces the resolution of the PWM output but increases the maximum output rate of the PWM (e.g.
ADuC834 Mode 4: Dual NRZ 16-Bit - DAC PWM1L PWM COUNTERS Mode 4 provides a high speed PWM output similar to that of a Σ-∆ DAC. Typically, this mode will be used with the PWM clock equal to 12.58 MHz. PWM1H PWM0L In this mode, P1.0 and P1.1 are updated every PWM clock (80 ns in the case of 12.58 MHz). Over any 65536 cycles (16-bit PWM) PWM0 (P1.0) is high for PWM0H/L cycles and low for (65536 – PWM0H/L) cycles. Similarly PWM1 (P1.1) is high for PWM1H/L cycles and low for (65536 – PWM1H/L) cycles.
ADuC834 ON-CHIP PLL The ADuC834 is intended for use with a 32.768 kHz watch crystal. A PLL locks onto a multiple (384) of this to provide a stable 12.582912 MHz clock for the system. The core can operate at this frequency, or at binary submultiples of it, to allow power saving in cases where maximum core performance is not PLLCON SFR Address Power-On Default Value Bit Addressable required. The default core clock is the PLL clock divided by 8 or 1.572864 MHz.
ADuC834 TIME INTERVAL COUNTER (WAKE-UP/RTC TIMER) A time interval counter (TIC) is provided on-chip for: • periodically waking the part up from power-down • implementing a Real-Time Clock • counting longer intervals than the standard 8051 compatible timers are capable of sheet.) If the ADuC834 is in power-down mode, again with TIC interrupt enabled, the TII bit will wake up the device and resume code execution by vectoring directly to the TIC interrupt service vector address at 0053H.
ADuC834 INTVAL User Time Interval Select Register Function SFR Address Power-On Default Value Reset Default Value Bit Addressable Valid Value User code writes the required time interval to this register. When the 8-bit interval counter is equal to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON.2) is set and generates generates an interrupt if enabled. (See IEIP2 SFR description under Interrupt System in this data sheet.
ADuC834 WATCHDOG TIMER The purpose of the watchdog timer is to generate a device reset or interrupt within a reasonable amount of time if the ADuC834 enters an erroneous state, possibly due to a programming error, electrical noise, or RFI. The watchdog function can be disabled by clearing the WDE (Watchdog Enable) bit in the Watchdog Control (WDCON) SFR.
ADuC834 POWER SUPPLY MONITOR As its name suggests, the Power Supply Monitor, once enabled, monitors both supplies (AVDD or DVDD) on the ADuC834. It will indicate when any of the supply pins drop below one of four user-selectable voltage trip points from 2.63 V to 4.63 V. For correct operation of the Power Supply Monitor function, AVDD must be equal to or greater than 2.7 V. Monitor function is controlled via the PSMCON SFR.
ADuC834 SERIAL PERIPHERAL INTERFACE MISO (Master In, Slave Out Data I/O Pin), Pin 14 The ADuC834 integrates a complete hardware Serial Peripheral Interface (SPI) interface on-chip. SPI is an industry-standard synchronous serial interface that allows eight bits of data to be synchronously transmitted and received simultaneously, i.e., full duplex. It should be noted that the SPI pins SCLOCK and MOSI are multiplexed with the I2C pins SCLOCK and SDATA.
ADuC834 SPIDAT SPI Data Register Function The SPIDAT SFR is written by the user to transmit data over the SPI interface or read by user code to read data just received by the SPI interface. F7H 00H No SFR Address Power-On Default Value Bit Addressable Using the SPI Interface SPI Interface—Master Mode Depending on the configuration of the bits in the SPICON SFR shown in Table XXI, the ADuC834 SPI interface will transmit or receive data in a number of possible modes.
ADuC834 I2C SERIAL INTERFACE The ADuC834 supports a fully licensed* I2C serial interface. The I2C interface is implemented as a full hardware slave and software master. SDATA (Pin 27) is the data I/O pin and SCLOCK (Pin 26) is the serial clock. These two pins are shared with the MOSI and SCLOCK pins of the on-chip SPI interface. Therefore the user can only enable one or the other interface at any given time (see SPE in Table XXI).
ADuC834 Once enabled in I2C slave mode, the slave controller waits for a START condition. If the ADuC834 detects a valid start condition, followed by a valid address, and by the R/W bit, the I2CI interrupt bit will get automatically set by hardware. The main features of the MicroConverter I2C interface are: • Only two bus lines are required; a serial data line (SDATA) and a serial clock line (SCLOCK). • An I2C master can communicate with multiple slave devices.
ADuC834 DUAL DATA POINTER The ADuC834 incorporates two data pointers. The second data pointer is a shadow data pointer and is selected via the data pointer control SFR (DPCON). DPCON also includes features such as automatic hardware post-increment and post-decrement, as well as automatic data pointer toggle. DPCON is described in Table XXIII. DPCON SFR Address Power-On Default Value Bit Addressable Data Pointer Control SFR A7H 00H No Table XXIII.
ADuC834 8052 COMPATIBLE ON-CHIP PERIPHERALS Port 1 This section gives a brief overview of the various secondary peripheral circuits that are also available to the user on-chip. These remaining functions are mostly 8052 compatible (with a few additional features) and are controlled via standard 8052 SFR bit definitions. Port 1 is also an 8-bit port directly controlled via the P1 SFR. The Port 1 pins are divided into two distinct pin groupings P1.0 to P1.1 and P1.2 to P1.7. P1.0 and P1.1 P1.0 and P1.
ADuC834 P1.2 to P1.7 The remaining Port 1 pins (P1.2–P1.7) can only be configured as analog input (ADC) or digital input pins. By (power-on) default, these pins are configured as analog inputs, i.e., ‘1’ written in the corresponding Port 1 register bit. To configure any of these pins as digital inputs, the user should write a ‘0’ to these port bits to configure the corresponding pin as a high impedance digital input. Figure 39 illustrates this function.
ADuC834 Notice also that direct access to the SCLOCK and SDATA/MOSI pins is afforded through the SFR interface in I2C master mode. Therefore, if you are not using the SPI or I2C functions, you can use these two pins to give additional high current digital outputs. DVDD SPE = 1 (SPI ENABLE) As shown in Figure 46, the MISO pin in SPI master/slave operation offers the exact same pull-up and pull-down configuration as the MOSI pin in SPI slave/master operation.
ADuC834 In ‘Timer’ function, the TLx Register is incremented every machine cycle. Thus it can be viewed as counting machine cycles. Since a machine cycle consists of 12 core clock periods, the maximum count rate is 1/12 of the core clock frequency. S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected.
ADuC834 TCON Timer/Counter 0 and 1 Control Register SFR Address Power-On Default Value Bit Addressable 88H 00H Yes Table XXVII. TCON SFR Bit Designations Bit Name Description 7 TF1 Timer 1 Overflow Flag. Set by hardware on a Timer/Counter 1 overflow. Cleared by hardware when the Program Counter (PC) vectors to the interrupt service routine. 6 TR1 Timer 1 Run Control Bit. Set by user to turn on Timer/Counter 1. Cleared by user to turn off Timer/Counter 1. 5 TF0 Timer 0 Overflow Flag.
ADuC834 TIMER/COUNTER 0 AND 1 OPERATING MODES Mode 2 (8-Bit Timer/Counter with Auto Reload) The following paragraphs describe the operating modes for Timer/Counters 0 and 1. Unless otherwise noted, it should be assumed that these modes of operation are the same for Timer 0 as for Timer 1. Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload, as shown in Figure 50.
ADuC834 TIMER/COUNTER 2 OPERATING MODES 16-Bit Capture Mode The following paragraphs describe the operating modes for Timer/Counter 2. The operating modes are selected by bits in the T2CON SFR as shown in Table XXIX. In the Capture Mode, there are again two options, selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter that, upon overflowing, sets bit TF2, the Timer 2 overflow bit, which can be used to generate an interrupt.
ADuC834 T2CON Timer/Counter 2 Control Register SFR Address Power-On Default Value Bit Addressable C8H 00H Yes Table XXIX. T2CON SFR Bit Designations Bit Name Description 7 TF2 Timer 2 Overflow Flag. Set by hardware on a Timer 2 overflow. TF2 will not be set when either RCLK or TCLK = 1. Cleared by user software. 6 EXF2 Timer 2 External Flag. Set by hardware when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. Cleared by user software.
ADuC834 RxD(P3.0) and TxD(P3.1), while the SFR interface to the UART comprises the following registers: UART SERIAL INTERFACE The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. However, if the first byte still has not been read by the time reception of the second byte is complete, the first byte will be lost.
ADuC834 Mode 1: 8-Bit UART, Variable Baud Rate Mode 1 is selected by clearing SM0 and setting SM1. Each data byte (LSB first) is preceded by a start bit (0) and followed by a stop bit (1). Therefore 10 bits are transmitted on TxD or received on RxD. The baud rate can be set by Timer 1 or Timer 2 (or both). Alternatively, a dedicated baud rate generator, Timer 3, is provided on-chip to generate high speed, very accurate baud rates. Transmission is initiated by writing to SBUF.
ADuC834 BAUD RATE GENERATION USING TIMER 1 AND TIMER 2 Timer 1 Generated Baud Rates Timer 2 Generated Baud Rates Baud rates can also be generated using Timer 2. Using Timer 2 is similar to using Timer 1 in that the timer must overflow 16 times before a bit is transmitted/received. Because Timer 2 has a 16-bit Autoreload Mode, a wider range of baud rates is possible using Timer 2.
ADuC834 BAUD RATE GENERATION USING TIMER 3 The high integer dividers in a UART block means that high speed baud rates are not always possible using some particular crystals. e.g., using a 12 MHz crystal, a baud rate of 115200 is not possible. To address this problem the ADuC834 has added a dedicated baud rate timer (Timer 3) specifically for generating highly accurate baud rates.
ADuC834 INTERRUPT SYSTEM The ADuC834 provides a total of 11 interrupt sources with two priority levels. The control and configuration of the interrupt system is carried out through three interrupt-related SFRs. These are the IE (Interrupt Enable) Register, the IP (Interrupt Priority Register) and the IEIP2 (Secondary Interrupt Enable/Priority SFR) Registers. Their bit definitions are given in the Tables XXXV – XXXVII.
ADuC834 Interrupt Priority Interrupt Vectors The Interrupt Enable registers are written by the user to enable individual interrupt sources, while the Interrupt Priority registers allow the user to select one of two priority levels for each interrupt. An interrupt of a high priority may interrupt the service routine of a low priority interrupt, and if two interrupts of different priority occur at the same time, the higher level interrupt will be serviced first.
ADuC834 Though both external program memory and external data memory are accessed using some of the same pins, the two are completely independent of each other from a software point of view. For example, the chip can read/write external data memory while executing from external program memory. ADuC834 HARDWARE DESIGN CONSIDERATIONS This section outlines some of the key hardware design considerations that must be addressed when integrating the ADuC834 into any hardware system.
ADuC834 Power Supplies The ADuC834’s operational power supply voltage range is 2.7 V to 5.25 V. Although the guaranteed data sheet specifications are given only for power supplies within 2.7 V to 3.6 V or 5% of the nominal 5 V level, the chip will function equally well at any power supply level between 2.7 V and 5.25 V. Separate analog and digital power supply pins (AVDD and DVDD respectively) allow AVDD to be kept relatively free of noisy digital signals often present on the system DVDD line.
ADuC834 Power Saving Modes Wake-Up from Power-Down Latency Setting the Idle and Power-Down Mode Bits, PCON.0 and PCON.1 respectively, in the PCON SFR described in Table II allows the chip to be switched from Normal mode into Idle mode, and also into full Power-Down mode. Even with the 32 kHz crystal enabled during power-down, the PLL will take some time to lock after a wake-up from powerdown. Typically, the PLL will take about 1 ms to lock.
ADuC834 a. PLACE ANALOG COMPONENTS HERE The CHIPID SFR is a read-only register located at SFR address C2H. The upper nibble of this SFR designates the MicroConverter within the Σ-∆ ADC family. User software can read this SFR to identify the host MicroConverter and thus execute slightly different code if required. The CHIPID SFR reads as follows for the Σ-∆ ADC family of MicroConverter products. PLACE DIGITAL COMPONENTS HERE AGND DGND ADuC836 ADuC834 ADuC824 ADuC816 b.
ADuC834 OTHER HARDWARE CONSIDERATIONS In-Circuit Serial Download Access Embedded Serial Port Debugger Nearly all ADuC834 designs will want to take advantage of the in-circuit reprogrammability of the chip. This is accomplished by a connection to the ADuC834’s UART, which requires an external RS-232 chip for level translation if downloading code from a PC. Basic configuration of an RS-232 connection is illustrated in Figure 66 with a simple ADM3202-based circuit.
ADuC834 resistance. This differential voltage is routed directly to the positive and negative inputs of the primary ADC (AIN1, AIN2 respectively). The same current that excited the RTD also flows through a series resistance RREF generating a ratiometric voltage reference VREF.
ADuC834 Hardware: ADuC834 Evaluation Board, and Serial Port Cable Download—In Circuit Downloader The Serial Downloader is a software program that allows the user to serially download an assembled program (Intel Hex format file) to the on-chip program FLASH memory via the serial COM1 port on a standard PC. An Application Note (uC004) detailing this serial download protocol is available from www.analog.com/ microconverter.
ADuC834 (AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V; MIN to TMAX, unless otherwise noted.) TIMING SPECIFICATIONS1, 2, 3 all specifications T 32.768 kHz External Crystal Min Typ Max Parameter CLOCK INPUT (External Clock Driven XTAL1) XTAL1 Period tCK tCKL XTAL1 Width Low XTAL1 Width High tCKH XTAL1 Rise Time tCKR tCKF XTAL1 Fall Time ADuC834 Core Clock Frequency4 1/tCORE ADuC834 Core Clock Period5 tCORE tCYC ADuC834 Machine Cycle Time6 30.52 6.26 6.26 9 9 0.
ADuC834 Parameter EXTERNAL PROGRAM MEMORY ALE Pulsewidth tLHLL Address Valid to ALE Low tAVLL tLLAX Address Hold after ALE Low ALE Low to Valid Instruction In tLLIV ALE Low to PSEN Low tLLPL tPLPH PSEN Pulsewidth PSEN Low to Valid Instruction In tPLIV Input Instruction Hold after PSEN tPXIX tPXIZ Input Instruction Float after PSEN Address to Valid Instruction In tAVIV PSEN Low to Address Float tPLAZ tPHAX Address Hold after PSEN High 12.
ADuC834 12.
ADuC834 Parameter 12.
ADuC834 Parameter 12.58 MHz Core_Clk Min Typ Max UART TIMING (Shift Register Mode) Serial Port Clock Cycle Time tXLXL Output Data Setup to Clock tQVXH tDVXH Input Data Setup to Clock Input Data Hold after Clock tXHDX tXHQX Output Data Hold after Clock 662 292 0 42 Min Variable Core_Clk Typ Max 0.
ADuC834 Parameter Min SPI MASTER MODE TIMING (CPHA = 1) tSL SCLOCK Low Pulsewidth* tSH SCLOCK High Pulsewidth* Data Output Valid after SCLOCK Edge tDAV Data Input Setup Time before SCLOCK Edge tDSU Data Input Hold Time after SCLOCK Edge tDHD tDF Data Output Fall Time Data Output Rise Time tDR SCLOCK Rise Time tSR tSF SCLOCK Fall Time Typ Max 630 630 50 100 100 10 10 10 10 25 25 25 25 Unit Figure ns ns ns ns ns ns ns ns ns 75 75 75 75 75 75 75 75 75 *Characterized under the following conditions: C
ADuC834 Parameter Min SPI MASTER MODE TIMING (CPHA = 0) tSL SCLOCK Low Pulsewidth* tSH SCLOCK High Pulsewidth* Data Output Valid after SCLOCK Edge tDAV Data Output Setup before SCLOCK Edge tDOSU Data Input Setup Time before SCLOCK Edge tDSU tDHD Data Input Hold Time after SCLOCK Edge Data Output Fall Time tDF Data Output Rise Time tDR tSR SCLOCK Rise Time tSF SCLOCK Fall Time Typ Max 630 630 50 150 100 100 10 10 10 10 25 25 25 25 Unit Figure ns ns ns ns ns ns ns ns ns ns 76 76 76 76 76 76 76 76 76
ADuC834 Parameter Min SPI SLAVE MODE TIMING (CPHA = 1) tSS SS to SCLOCK Edge tSL SCLOCK Low Pulsewidth SCLOCK High Pulsewidth tSH Data Output Valid after SCLOCK Edge tDAV Data Input Setup Time before SCLOCK Edge tDSU tDHD Data Input Hold Time after SCLOCK Edge Data Output Fall Time tDF Data Output Rise Time tDR tSR SCLOCK Rise Time SCLOCK Fall Time tSF tSFS SS High after SCLOCK Edge Typ Max 0 330 330 50 100 100 10 10 10 10 25 25 25 25 0 SS tSFS tSS SCLOCK (CPOL = 0) tSL tSH tSR tSF SCLOCK (CP
ADuC834 Parameter Min SPI SLAVE MODE TIMING (CPHA = 0) SS to SCLOCK Edge tSS SCLOCK Low Pulsewidth tSL SCLOCK High Pulsewidth tSH tDAV Data Output Valid after SCLOCK Edge Data Input Setup Time before SCLOCK Edge tDSU Data Input Hold Time after SCLOCK Edge tDHD tDF Data Output Fall Time Data Output Rise Time tDR SCLOCK Rise Time tSR tSF SCLOCK Fall Time SS to SCLOCK Edge tSSR Data Output Valid after SS Edge tDOSS tSFS SS High after SCLOCK Edge Typ Max 0 330 330 50 100 100 10 10 10 10 25 25 25 25 50 20
ADuC834 Parameter Min Max Unit Figure µs µs µs ns µs µs µs µs 79 79 79 79 79 79 79 79 ns ns ns 79 79 79 2 I C-SERIAL INTERFACE TIMING tL SCLOCK Low Pulsewidth SCLOCK High Pulsewidth tH Start Condition Hold Time tSHD tDSU Data Setup Time Data Hold Time tDHD Setup Time for Repeated Start tRSU tPSU Stop Condition Setup Time Bus Free Time between a STOP tBUF Condition and a START Condition Rise Time of Both SCLOCK and SDATA tR Fall Time of Both SCLOCK and SDATA tF tSUP* Pulsewidth of Spike Suppressed
ADuC834 OUTLINE DIMENSIONS 52-Lead Metric Quad Flat Package [MQFP] (S-52) Dimensions shown in millimeters 14.15 13.90 SQ 13.65 2.45 MAX 39 27 40 SEATING PLANE C02942–0–4/03(A) 1.03 0.88 0.73 26 7.80 REF 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) VIEW A PIN 1 52 14 1 0.23 0.11 13 0.65 BSC 0.38 0.22 2.10 2.00 1.95 7 0 0.