MicroConverter® 12-Bit ADCs and DACs with Embedded High Speed 62-kB Flash MCU ADuC841/ADuC842/ADuC843 FUNCTIONAL BLOCK DIAGRAM FEATURES Analog I/O 8-channel, 420 kSPS high accuracy, 12-bit ADC On-chip, 15 ppm/°C voltage reference DMA controller, high speed ADC-to-RAM capture Two 12-bit voltage output DACs1 Dual output PWM ∑-∆ DACs On-chip temperature monitor function 8052 based core 8051 compatible instruction set (20 MHz max) High performance single-cycle core 32 kHz external crystal, on-chip programmabl
ADuC841/ADuC842/ADuC843 TABLE OF CONTENTS Specifications..................................................................................... 3 Pulse-Width Modulator (PWM).............................................. 42 Absolute Maximum Ratings............................................................ 8 Serial Peripheral Interface (SPI)............................................... 45 ESD Caution..................................................................................
ADuC841/ADuC842/ADuC843 SPECIFICATIONS1 Table 1. AVDD = DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V; VREF = 2.5 V internal reference, fCORE = 16.78 MHz @ 5 V 8.
ADuC841/ADuC842/ADuC843 Parameter DAC AC CHARACTERISTICS Voltage Output Settling Time Digital-to-Analog Glitch Energy DAC CHANNEL SPECIFICATIONS12, 13 Internal Buffer Disabled ADuC841/ADuC842 Only DC ACCURACY10 Resolution Relative Accuracy Differential Nonlinearity11 Offset Error Gain Error Gain Error Mismatch4 ANALOG OUTPUTS Voltage Range_0 REFERENCE INPUT/OUTPUT REFERENCE OUTPUT14 Output Voltage (VREF) Accuracy Power Supply Rejection Reference Temperature Coefficient Internal VREF Power-On Time EXTERNAL R
ADuC841/ADuC842/ADuC843 Parameter LOGIC INPUTS4 INPUT VOLTAGES All Inputs Except SCLOCK, SDATA, RESET, and XTAL1 VINL, Input Low Voltage VINH, Input High Voltage SDATA VINL, Input Low Voltage VINH, Input High Voltage SCLOCK and RESET Only4 (Schmitt-Triggered Inputs) VT+ VT– VT+ – VT– CRYSTAL OSCILLATOR Logic Inputs, XTAL1 Only VINL, Input Low Voltage VINH, Input High Voltage XTAL1 Input Capacitance XTAL2 Output Capacitance MCU CLOCK RATE DIGITAL OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) AL
ADuC841/ADuC842/ADuC843 Parameter POWER REQUIREMENTS19, 20 Power Supply Voltages AVDD/DVDD – AGND VDD = 5 V VDD = 3 V Unit Test Conditions/Comments 2.7 3.6 V min V max V min V max AVDD/DVDD = 3 V nom 4.75 5.
ADuC841/ADuC842/ADuC843 1 Temperature Range –40°C to +85°C. ADC linearity is guaranteed during normal MicroConverter core operation. 3 ADC LSB size = VREF/212, i.e., for internal VREF = 2.5 V, 1 LSB = 610 µV, and for external VREF = 1 V, 1 LSB = 244 µV. 4 These numbers are not production tested but are supported by design and/or characterization data on production release. 5 Offset and gain error and offset and gain error match are measured after factory calibration.
ADuC841/ADuC842/ADuC843 ABSOLUTE MAXIMUM RATINGS Table 2.
ADuC841/ADuC842/ADuC843 VREF SDATA/MOSI P0.1/AD1 P0.0/AD0 ALE PSEN 47 46 45 44 43 EA P0.2/AD2 48 P2.5/A13/A21 39 P2.4/A12/A20 DGND 12 P1.4/ADC4 P1.5/ADC5/SS 13 16 *EXTCLK NOT PRESENT ON THE ADuC841 DGND DVDD P2.1/A9/A17 P2.0/A8/A16 SDATA/MOSI 28 15 P.7/ADC7 14 27 P2.2/A10/A18 DAC1 32 31 30 29 P3.7/RD SCLOCK P2.3/A11/A19 11 26 33 DAC0 9 P3.6/WR 10 25 XTAL2 XTAL1 P3.
ADuC841/ADuC842/ADuC843 Mnemonic P3.0–P3.7 Type I/O PWMC PWM0 PWM1 RxD TxD INT0 I O O I/O O I INT1 I T0 T1 CONVST I I I EXTCLK WR RD XTAL2 XTAL1 DGND P2.0–P2.7 (A8–A15) (A16–A23) I O O O I G I/O PSEN O ALE O EA I P0.7–P0.0 (A0-A7) I/O Function Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs.
ADuC841/ADuC842/ADuC843 TERMINOLOGY ADC SPECIFICATIONS DAC SPECIFICATIONS Integral Nonlinearity Relative Accuracy The maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point ½ LSB below the first code transition, and full scale, a point ½ LSB above the last code transition.
ADuC841/ADuC842/ADuC843 TYPICAL PERFORMANCE CHARACTERISTICS The typical performance plots presented in this section illustrate typical performance of the ADuC841/ADuC842/ ADuC843 under various operating conditions. Figure 5 and Figure 6 show typical ADC integral nonlinearity (INL) errors from ADC Code 0 to Code 4095 at 5 V and 3 V supplies, respectively. The ADC is using its internal reference (2.
ADuC841/ADuC842/ADuC843 0.8 1.0 0.8 0.6 0.8 AVDD/DVDD = 3V AVDD/DVDD = 5V fS = 400kHz CD = 4 fS = 152kHz 0.6 0.4 0.6 WCP INL 0.4 LSBs 0.2 0 –0.2 0.2 0.2 0 0 –0.2 –0.2 WCN–INL (LSBs) WCP–INL (LSBs) 0.4 –0.4 WCN INL –0.4 –0.4 –0.6 –0.6 0 511 1023 1535 2047 2559 ADC CODES 3071 3583 4095 –0.6 –0.8 –0.8 0.5 Figure 7. Typical INL Error, VDD = 5 V, fS = 400 kHz 1.5 2.5 1.0 2.0 EXTERNAL REFERENCE (V) 3.0 Figure 10. Typical Worst-Case INL Error vs. VREF, VDD = 3 V 1.0 1.
ADuC841/ADuC842/ADuC843 10000 0.6 0.6 AVDD /DVDD = 5V fS = 152kHz 9000 0.4 0.4 WCP DNL 0.2 0 0 –0.2 –0.2 7000 OCCURRENCE 0.2 WCN–DNL (LSBs) WCP–DNL (LSBs) 8000 6000 5000 4000 3000 WCN DNL –0.4 –0.4 –0.6 –0.6 2000 5.0 0 817 Figure 13. Typical Worst-Case DNL Error vs. VREF, VDD = 5 V AVDD/DVDD = 3V fS = 152kHz 0.5 820 821 AVDD/DVDD = 5V fS = 152kHz fIN = 9.910kHz SNR = 71.3dB THD = –88.0dB ENOB = 11.6 0 –20 0.1 0.1 –0.1 WCN DNL –0.3 –0.3 –0.5 –0.5 –0.7 –0.
ADuC841/ADuC842/ADuC843 –70 80 AVDD /DVDD = 5V fS = 152kHz 75 80 AVDD /DVDD = 5V 78 –75 76 –80 65 –85 74 THD 60 –90 55 –95 SNR (dBs) 70 THD (dBs) SNR (dBs) SNR 72 70 68 66 64 400.000 350.000 300.000 226.190 199.410 172.620 60 145.830 5.0 119.050 1.0 1.5 2.0 2.5 EXTERNAL REFERENCE (V) 92.262 0.5 65.476 –100 50 03260-0-019 03260-0-017 62 FREQUENCY (kHz) Figure 19. Typical Dynamic Performance vs. VREF, VDD = 5 V Figure 21. Typical Dynamic Performance vs.
ADuC841/ADuC842/ADuC843 FUNCTIONAL DESCRIPTION 8052 INSTRUCTION SET Table 4 documents the number of clock cycles required for each instruction. Most instructions are executed in one or two clock cycles, resulting in a 16 MIPS peak performance when operating at PLLCON = 00H on the ADuC842/ADuC843. On the ADuC841, 20 MIPS peak performance is possible with a 20 MHz external crystal. Table 4.
ADuC841/ADuC842/ADuC843 Mnemonic XRL A,dir XRL dir,#data CLR A CPL A SWAP A RL A RLC A RR A RRC A Data Transfer MOV A,Rn MOV A,@Ri MOV Rn,A MOV @Ri,A MOV A,dir MOV A,#data MOV Rn,#data MOV dir,A MOV Rn, dir MOV dir, Rn MOV @Ri,#data MOV dir,@Ri MOV @Ri,dir MOV dir,dir MOV dir,#data MOV DPTR,#data MOVC A,@A+DPTR MOVC A,@A+PC MOVX A,@Ri MOVX A,@DPTR MOVX @Ri,A MOVX @DPTR,A PUSH dir POP dir XCH A,Rn XCH A,@Ri XCHD A,@Ri XCH A,dir Boolean CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C,bit ANL C,/bit ORL C,bi
ADuC841/ADuC842/ADuC843 Mnemonic Branching JMP @A+DPTR RET RETI ACALL addr11 AJMP addr11 SJMP rel JC rel JNC rel JZ rel JNZ rel DJNZ Rn,rel LJMP LCALL addr16 JB bit,rel JNB bit,rel JBC bit,rel CJNE A,dir,rel CJNE A,#data,rel CJNE Rn,#data,rel CJNE @Ri,#data,rel DJNZ dir,rel Miscellaneous NOP Description Bytes Cycles Jump indirect relative to DPTR Return from subroutine Return from interrupt Absolute jump to subroutine Absolute jump unconditional Short jump (relative address) Jump on carry equal to 1 Jum
ADuC841/ADuC842/ADuC843 MEMORY ORGANIZATION The ADuC841/ADuC842/ADuC843 each contain four different memory blocks: • Up to 62 kBytes of on-chip Flash/EE program memory • 4 kBytes of on-chip Flash/EE data memory • 256 bytes of general-purpose RAM • 2 kBytes of internal XRAM Flash/EE Program Memory The parts provide up to 62 kBytes of Flash/EE program memory to run user code. The user can run code from this internal memory only.
ADuC841/ADuC842/ADuC843 07FFH FFFFFFH FFFFFFH UPPER 1792 BYTES OF ON-CHIP XRAM (DATA + STACK FOR EXSP = 1, DATA ONLY FOR EXSP = 0) CFG841.7 = 1 CFG842.7 = 1 EXTERNAL DATA MEMORY SPACE (24-BIT ADDRESS SPACE) 000800H 100H FFH LOWER 256 BYTES OF ON-CHIP XRAM (DATA ONLY) 00H 03260-0-022 00H 256 BYTES OF ON-CHIP DATA RAM (DATA + STACK) 0007FFH 000000H 000000H CFG841.0 = 0 CFG842.0 = 0 2 kBYTES ON-CHIP XRAM CFG841.0 = 1 CFG842.0 = 0 03260-0-023 CFG841.7 = 0 CFG842.
ADuC841/ADuC842/ADuC843 ACCUMULATOR SFR (ACC) Program Status Word (PSW) ACC is the accumulator register and is used for math operations including addition, subtraction, integer multiplication and division, and Boolean bit manipulations. The mnemonics for accumulator-specific instructions refer to the accumulator as A. The PSW SFR contains several bits reflecting the current status of the CPU, as detailed in Table 5.
ADuC841/ADuC842/ADuC843 SPECIAL FUNCTION REGISTER BANKS implemented, i.e., no register exists at this location. If an unoccupied location is read, an unspecified value is returned. SFR locations reserved for on-chip testing are shown lighter shaded (RESERVED) and should not be accessed by user software. Sixteen of the SFR locations are also bit addressable and denoted by 1 in Figure 27, i.e., the bit addressable SFRs are those whose address ends in 0H or 8H.
ADuC841/ADuC842/ADuC843 ADC CIRCUIT INFORMATION General Overview ADC Transfer Function The ADC conversion block incorporates a fast, 8-channel, 12-bit, single-supply ADC. This block provides the user with multichannel mux, track-and-hold, on-chip reference, calibration features, and ADC. All components in this block are easily configured via a 3-register SFR interface. The analog input range for the ADC is 0 V to VREF.
ADuC841/ADuC842/ADuC843 ADCCON1—(ADC Control SFR 1) The ADCCON1 register controls conversion and acquisition times, hardware conversion modes, and power-down modes as detailed below. SFR Address EFH SFR Power-On Default 40H Bit Addressable No Table 7. ADCCON1 SFR Bit Designations Bit No. 7 Name MD1 6 EXT_REF 5 4 CK1 CK0 3 2 AQ1 AQ0 1 T2C 0 EXC Description The mode bit selects the active operating mode of the ADC. Set by the user to power up the ADC.
ADuC841/ADuC842/ADuC843 ADCCON2—(ADC Control SFR 2) The ADCCON2 register controls ADC channel selection and conversion modes as detailed below. SFR Address D8H SFR Power-On Default 00H Bit Addressable Yes Table 8. ADCCON2 SFR Bit Designations Bit No. 7 Name ADCI 6 DMA 5 CCONV 4 SCONV 3 2 1 0 CS3 CS2 CS1 CS0 Description ADC Interrupt Bit. Set by hardware at the end of a single ADC conversion cycle or at the end of a DMA block conversion.
ADuC841/ADuC842/ADuC843 ADCCON3—(ADC Control SFR 3) The ADCCON3 register controls the operation of various calibration modes and also indicates the ADC busy status. SFR Address F5H SFR Power-On Default 00H Bit Addressable No Table 9. ADCCON3 SFR Bit Designations Bit No. 7 Name BUSY 6 5 4 RSVD AVGS1 AVGS0 3 2 1 RSVD RSVD TYPICAL 0 SCAL Description ADC Busy Status Bit. A read-only status bit that is set during a valid ADC conversion or during a calibration cycle.
ADuC841/ADuC842/ADuC843 ADuC841/ADuC842/ADuC843 VREF AGND DAC1 DAC0 TEMPERATURE MONITOR AIN7 CAPACITOR DAC 200Ω AIN0 sw1 HOLD COMPARATOR 32pF 200Ω sw2 TRACK ADuC841/ ADuC842/ ADuC843 10Ω AIN0 0.1µ F Figure 31. Buffering Analog Inputs It does so by providing a capacitive bank from which the 32 pF sampling capacitor can draw its charge. Its voltage does not change by more than one count (1/4096) of the 12-bit transfer function when the 32 pF charge from a previous channel is dumped onto it.
ADuC841/ADuC842/ADuC843 Table 11. Some Single-Supply Op Amps Op Amp Model OP281/OP481 OP191/OP291/OP491 OP196/OP296/OP496 OP183/OP283 OP162/OP262/OP462 AD820/AD822/AD824 AD823 If an external voltage reference is preferred, it should be connected to the CREF pin as shown in Figure 33. Bit 6 of the ADCCON1 SFR must be set to 1 to switch in the external reference voltage.
00000AH Increasing the conversion time on the temperature monitor channel improves the accuracy of the reading. To further improve the accuracy, an external reference with low temperature drift should also be used. ADC DMA Mode 000000H The on-chip ADC has been designed to run at a maximum conversion speed of 2.38 µs (420 kHz sampling rate).
ADuC841/ADuC842/ADuC843 The DMA logic operates from the ADC clock and uses pipelining to perform the ADC conversions and to access the external memory at the same time. The time it takes to perform one ADC conversion is called a DMA cycle. The actions performed by the logic during a typical DMA cycle are shown in Figure 36.
ADuC841/ADuC842/ADuC843 Initiating the Calibration in Code NONVOLATILE FLASH/EE MEMORY When calibrating the ADC using ADCCON1, the ADC must be set up into the configuration in which it will be used. The ADCCON3 register can then be used to set up the device and to calibrate the ADC offset and gain. The ADuC841/ADuC842/ADuC843 incorporate Flash/EE memory technology on-chip to provide the user with nonvolatile, in-circuit, reprogrammable code and data memory space.
ADuC841/ADuC842/ADuC843 The Flash/EE program and data memory arrays on the parts are fully qualified for two key Flash/EE memory characteristics: Flash/EE memory cycling endurance and Flash/EE memory data retention. 250 Initial page erase sequence. 2. Read/verify sequence a single Flash/EE. 3. Byte program sequence memory. 4. Second read/verify sequence endurance cycle. ADI SPECIFICATION 100 YEARS MIN.
ADuC841/ADuC842/ADuC843 EMBEDDED DOWNLOAD/DEBUG KERNEL PERMANENTLY EMBEDDED FIRMWARE ALLOWS CODE TO BE DOWNLOADED TO ANY OF THE 32 kBYTES OF ON-CHIP PROGRAM MEMORY. THE KERNEL PROGRAM APPEARS AS 'NOP' INSTRUCTIONS TO USER CODE Figure 39 shows that it is possible to use the 62 kBytes of Flash/EE program memory available to the user as a single block of memory. In this mode, all of the Flash/EE memory is read-only to user code.
ADuC841/ADuC842/ADuC843 BYTE 4 (0FFFH) 3FEH BYTE 1 (0FF8H) BYTE 2 (0FF9H) BYTE 3 (0FFAH) BYTE 4 (0FFBH) 03H BYTE 1 (000CH) BYTE 2 (000DH) BYTE 3 (000EH) BYTE 4 (000FH) 02H BYTE 1 (0008H) BYTE 2 (0009H) BYTE 3 (000AH) BYTE 4 (000BH) 01H BYTE 1 (0004H) BYTE 2 (0005H) BYTE 3 (0006H) BYTE 4 (0007H) 00H BYTE 1 (0000H) BYTE 2 (0001H) BYTE 3 (0002H) BYTE 4 (0003H) BYTE ADDRESSES ARE GIVEN IN BRACKETS 03260-0-040 BYTE 3 (0FFEH) EDATA4 SFR BYTE 2 (0FFDH) EDATA3 SFR Programming of eith
ADuC841/ADuC842/ADuC843 Example: Programming the Flash/EE Data Memory Flash/EE Memory Timing A user wants to program F3H into the second byte on Page 03H of the Flash/EE data memory space while preserving the other 3 bytes already in this page. A typical program of the Flash/EE data array involves Typical program and erase times for the parts are as follows: 1. Setting EADRH/L with the page address. 2. Writing the data to be programmed to the EDATA1–4. 3.
ADuC841/ADuC842/ADuC843 ADuC842/ADuC843 Configuration SFR (CFG842) The CFG842 SFR contains the necessary bits to configure the internal XRAM, external clock select, PWM output selection, DAC buffer, and the extended SP for both the ADuC842 and the ADuC843. By default, it configures the user into 8051 mode, i.e., extended SP is disabled and internal XRAM is disabled. On the ADuC841, this register is the CFG841 register and is described on the next page.
ADuC841/ADuC842/ADuC843 CFG841 ADuC841 Config SFR SFR Address AFH Power-On Default 10H1 Bit Addressable No Table 14. CFG841 SFR Bit Designations Bit No. 7 Name EXSP 6 PWPO 5 DBUF 4 EPM2 3 2 EPM1 EPM0 1 MSPI 0 XRAMEN 1 Description Extended SP Enable. When set to 1 by the user, the stack rolls over from SPH/SP = 00FFH to 0100H. When set to 0 by the user, the stack rolls over from SP = FFH to SP = 00H. PWM Pin Out Selection. Set to 1 by the user to select P3.4 and P3.
ADuC841/ADuC842/ADuC843 USER INTERFACE TO ON-CHIP PERIPHERALS This section gives a brief overview of the various peripherals also available on-chip. A summary of the SFRs used to control and configure these peripherals is also given. DAC The ADuC841/ADuC842 incorporate two 12-bit voltage output DACs on-chip. Each has a rail-to-rail voltage output buffer capable of driving 10 kΩ/100 pF. Each has two selectable ranges, 0 V to VREF (the internal band gap 2.5 V reference) and 0 V to AVDD.
ADuC841/ADuC842/ADuC843 Using the DAC The on-chip DAC architecture consists of a resistor string DAC followed by an output buffer amplifier, the functional equivalent of which is illustrated in Figure 42. Details of the actual DAC architecture can be found in U.S. Patent Number 5969657 (www.uspto.gov). Features of this architecture include inherent guaranteed monotonicity and excellent differential linearity.
ADuC841/ADuC842/ADuC843 To reduce the effects of the saturation of the output amplifier at values close to ground and to give reduced offset and gain errors, the internal buffer can be bypassed. This is done by setting the DBUF bit in the CFG841/CFG842 register. This allows a full rail-to-rail output from the DAC, which should then be buffered externally using a dual-supply op amp in order to get a rail-torail output.
ADuC841/ADuC842/ADuC843 ON-CHIP PLL The ADuC842 and ADuC843 are intended for use with a 32.768 kHz watch crystal. A PLL locks onto a multiple (512) of this to provide a stable 16.78 MHz clock for the system. The ADuC841 operates directly from an external crystal. The core can operate at this frequency or at binary submultiples of it to allow power saving in cases where maximum core performance is not required. The default core clock is the PLL clock divided by 8 or 2.097152 MHz.
ADuC841/ADuC842/ADuC843 PULSE-WIDTH MODULATOR (PWM) The PWM on the ADuC841/ADuC842/ADuC843 is a highly flexible PWM offering programmable resolution and an input clock, and can be configured for any one of six different modes of operation. Two of these modes allow the PWM to be configured as a ∑-∆ DAC with up to 16 bits of resolution. A block diagram of the PWM is shown in Figure 47. Note the PWM clock’s sources are different for the ADuC841, and are given in Table 17.
ADuC841/ADuC842/ADuC843 PWM Modes of Operation PWM1L PWM COUNTER Mode 0: PWM Disabled The PWM is disabled allowing P2.6 and P2.7 to be used as normal. PWM0H Mode 1: Single Variable Resolution PWM PWM1H PWM0L 0 In Mode 1, both the pulse length and the cycle time (period) are programmable in user code, allowing the resolution of the PWM to be variable. PWM0H/L sets the duty cycle of the PWM output waveform, as shown in Figure 48.
ADuC841/ADuC842/ADuC843 PWM1L Mode 4: Dual NRZ 16-Bit ∑-∆ DAC PWM COUNTERS Mode 4 provides a high speed PWM output similar to that of a ∑-∆ DAC. Typically, this mode is used with the PWM clock equal to 16.777216 MHz. In this mode, P2.6 and P2.7 are updated every PWM clock (60 ns in the case of 16 MHz). Over any 65536 cycles (16-bit PWM) PWM0 (P2.6) is high for PWM0H/L cycles and low for (65536 – PWM0H/L) cycles. Similarly, PWM1 (P2.7) is high for PWM1H/L cycles and low for (65536 – PWM1H/L) cycles.
ADuC841/ADuC842/ADuC843 SERIAL PERIPHERAL INTERFACE (SPI) SCLOCK (Serial Clock I/O Pin) The ADuC841/ADuC842/ADuC843 integrate a complete hardware serial peripheral interface on-chip. SPI is an industrystandard synchronous serial interface that allows 8 bits of data to be synchronously transmitted and received simultaneously, i.e., full duplex. Note that the SPI pins are shared with the I2C pins.
ADuC841/ADuC842/ADuC843 SPICON SPI Control Register SFR Address F8H Power-On Default 04H Bit Addressable Yes Table 18. SPICON SFR Bit Designations Bit No. 7 Name ISPI 6 WCOL 5 SPE 4 SPIM 3 CPOL1 2 CPHA1 1 0 SPR1 SPR0 Description SPI Interrupt Bit. Set by the MicroConverter at the end of each SPI transfer. Cleared directly by user code or indirectly by reading the SPIDAT SFR. Write Collision Error Bit.
ADuC841/ADuC842/ADuC843 Using the SPI Interface Depending on the configuration of the bits in the SPICON SFR shown in Table 18, the ADuC841/ADuC842/ADuC843 SPI interface transmits or receives data in a number of possible modes. Figure 54 shows all possible SPI configurations for the parts, and the timing relationships and synchronization between the signals involved. Also shown in this figure is the SPI interrupt bit (ISPI) and how it is triggered at the end of each byte-wide communication.
ADuC841/ADuC842/ADuC843 I2C COMPATIBLE INTERFACE The ADuC841/ADuC842/ADuC843 support a fully licensed I2C serial interface. The I2C interface is implemented as a full hardware slave and software master. SDATA is the data I/O pin, and SCLOCK is the serial clock. These two pins are shared with the MOSI and SCLOCK pins of the on-chip SPI interface. To enable the I2C interface, the SPI interface must be turned off (see SPE in Table 18) or the SPI interface must be moved to P3.3, P3.4, and P3.5 via the CFG841.
ADuC841/ADuC842/ADuC843 Bit No. 2 Name I2CRS 1 I2CTX 0 I2CI Description I2C Reset Bit (Slave Mode Only). Set by the user to reset the I2C interface. Cleared by the user code for normal I2C operation. I2C Direction Transfer Bit (Slave Mode Only). Set by the MicroConverter if the interface is transmitting. Cleared by the MicroConverter if the interface is receiving. I2C Interrupt Bit (Slave Mode Only). Set by the MicroConverter after a byte has been transmitted or received.
ADuC841/ADuC842/ADuC843 • • An I2C slave can respond to repeated start conditions without a stop bit in between. This allows a master to change direction of transfer without giving up the bus. Note that the repeated start is detected only when a slave has previously been configured as a receiver. On-chip filtering rejects <50 ns spikes on the SDATA and the SCLOCK lines to preserve data integrity.
ADuC841/ADuC842/ADuC843 DUAL DATA POINTER The ADuC841/ADuC842/ADuC843 incorporate two data pointers. The second data pointer is a shadow data pointer and is selected via the data pointer control SFR (DPCON). DPCON also includes some useful features such as automatic hardware post-increment and post-decrement as well as automatic data pointer toggle. DPCON is described in Table 21. DPCON Data Pointer Control SFR SFR Address A7H Power-On Default 00H Bit Addressable No Table 21.
ADuC841/ADuC842/ADuC843 POWER SUPPLY MONITOR As its name suggests, the power supply monitor, once enabled, monitors the DVDD supply on the ADuC841/ADuC842/ ADuC843. It indicates when any of the supply pins drops below one of two user selectable voltage trip points, 2.93 V and 3.08 V. For correct operation of the power supply monitor function, AVDD must be equal to or greater than 2.7 V. Monitor function is controlled via the PSMCON SFR.
ADuC841/ADuC842/ADuC843 WATCHDOG TIMER The purpose of the watchdog timer is to generate a device reset or interrupt within a reasonable amount of time if the ADuC841/ ADuC842/ADuC843 enter an erroneous state, possibly due to a programming error or electrical noise. The watchdog function can be disabled by clearing the WDE (watchdog enable) bit in the watchdog control (WDCON) SFR.
ADuC841/ADuC842/ADuC843 TIME INTERVAL COUNTER (TIC) Six SFRs are associated with the time interval counter, TIMECON being its control register. Depending on the configuration of the IT0 and IT1 bits in TIMECON, the selected time counter register overflow clocks the interval counter. When this counter is equal to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON.2) is set and generates an interrupt if enabled.
ADuC841/ADuC842/ADuC843 TIMECON TIC Control Register SFR Address A1H Power-On Default 00H Bit Addressable No Table 24. TIMECON SFR Bit Designations Bit No. 7 6 Name ---TFH 5 4 ITS1 ITS0 3 STI 2 TII 1 TIEN 0 TCEN Description Reserved. Twenty-Four Hour Select Bit. Set by the user to enable the hour counter to count from 0 to 23. Cleared by the user to enable the hour counter to count from 0 to 255. Interval Timebase Selection Bits.
ADuC841/ADuC842/ADuC843 INTVAL Function User Time Interval Select Register User code writes the required time interval to this register. When the 8-bit interval counter is equal to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON.2) is set and generates an interrupt if enabled.
ADuC841/ADuC842/ADuC843 8052 COMPATIBLE ON-CHIP PERIPHERALS Parallel I/O The ADuC841/ADuC842/ADuC843 use four input/output ports to exchange data with external devices. In addition to performing general-purpose I/O, some ports are capable of external memory operations while others are multiplexed with alternate functions for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general-purpose I/O pin.
ADuC841/ADuC842/ADuC843 P2.6 and P2.7 can also be used as PWM outputs. When they are selected as the PWM outputs via the CFG841/CFG842 SFR, the PWM outputs overwrite anything written to P2.6 or P2.7. D WRITE TO LATCH CL WRITE TO LATCH D Q P2.x PIN DVDD Q2 03260-0-058 DVDD Q3 Q4 Px.x PIN 03260-0-059 DVDD Q1 P3.x PIN Q CL Q * SEE PREVIOUS FIGURE FOR DETAILS OF INTERNAL PULL-UP ALTERNATE INPUT FUNCTION Figure 61.
ADuC841/ADuC842/ADuC843 Read-Modify-Write Instructions MOSI is shared with P3.3 and, as such, has the same configuration as the one shown in Figure 61. DVDD SPE = 0 (I2C ENABLE) HARDWARE I2C (SLAVE ONLY) Q1 (OFF) Q2 50ns GLITCH REJECTION FILTER SFR BITS Some 8051 instructions that read a port read the latch while others read the pin. The instructions that read the latch rather than the pins are the ones that read a value, possibly change it, and then rewrite it to the latch.
ADuC841/ADuC842/ADuC843 Timers/Counters The ADuC841/ADuC842/ADuC843 have three 16-bit timer/ counters: Timer 0, Timer 1, and Timer 2. The timer/counter hardware is included on-chip to relieve the processor core of the overhead inherent in implementing timer/counter functionality in software. Each timer/counter consists of two 8-bit registers: THx and TLx (x = 0, 1, and 2). All three can be configured to operate either as timers or as event counters.
ADuC841/ADuC842/ADuC843 TCON Timer/Counter 0 and 1 Control Register SFR Address 88H Power-On Default 00H Bit Addressable Yes Table 29. TCON SFR Bit Designations Bit No. 7 Name TF1 6 TR1 5 TF0 4 TR0 3 IE11 2 IT11 1 IE01 0 IT01 Description Timer 1 Overflow Flag. Set by hardware on a Timer/Counter 1 overflow. Cleared by hardware when the program counter (PC) vectors to the interrupt service routine. Timer 1 Run Control Bit. Set by the user to turn on Timer/Counter 1.
ADuC841/ADuC842/ADuC843 TIMER/COUNTER 0 AND 1 OPERATING MODES Mode 2 (8-Bit Timer/Counter with Autoreload) The following sections describe the operating modes for Timer/Counters 0 and 1. Unless otherwise noted, assume that these modes of operation are the same for both Timer 0 and Timer 1. Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload, as shown in Figure 68.
ADuC841/ADuC842/ADuC843 T2CON Timer/Counter 2 Control Register SFR Address C8H Power-On Default 00H Bit Addressable Yes Table 30. T2CON SFR Bit Designations Bit No. 7 Name TF2 6 EXF2 5 RCLK 4 TCLK 3 EXEN2 2 TR2 1 CNT2 0 CAP2 Description Timer 2 Overflow Flag. Set by hardware on a Timer 2 overflow. TF2 cannot be set when either RCLK = 1 or TCLK = 1. Cleared by user software. Timer 2 External Flag.
ADuC841/ADuC842/ADuC843 TIMER/COUNTER OPERATING MODES 16-Bit Capture Mode The following sections describe the operating modes for Timer/Counter 2. The operating modes are selected by bits in the T2CON SFR, as shown in Table 31. 16-Bit Autoreload Mode Capture mode also has two options that are selected by bit EXEN2 in T2CON. If EXEN2 = 0, then Timer 2 is a 16-bit timer or counter that, upon overflowing, sets Bit TF2, the Timer 2 overflow bit, which can be used to generate an interrupt.
ADuC841/ADuC842/ADuC843 UART SERIAL INTERFACE SBUF The serial port is full-duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can begin receiving a second byte before a previously received byte has been read from the receive register. However, if the first byte still has not been read by the time reception of the second byte is complete, the first byte is lost. The physical interface to the serial data network is via Pins RxD(P3.0) and TxD(P3.
ADuC841/ADuC842/ADuC843 Mode 0: 8-Bit Shift Register Mode Mode 0 is selected by clearing both the SM0 and SM1 bits in the SFR SCON. Serial data enters and exits through RxD. TxD outputs the shift clock. Eight data bits are transmitted or received. Transmission is initiated by any instruction that writes to SBUF. The data is shifted out of the RxD line. The 8 bits are transmitted with the least significant bit (LSB) first.
ADuC841/ADuC842/ADuC843 Mode 3: 9-Bit UART with Variable Baud Rate Mode 3 is selected by setting both SM0 and SM1. In this mode, the 8051 UART serial port operates in 9-bit mode with a variable baud rate determined by either Timer 1 or Timer 2. The operation of the 9-bit UART is the same as for Mode 2, but the baud rate can be varied as for Mode 1. The Timer 1 interrupt should be disabled in this application.
ADuC841/ADuC842/ADuC843 Timer 3 Generated Baud Rates The high integer dividers in a UART block mean that high speed baud rates are not always possible using some particular crystals. For example, using a 12 MHz crystal, a baud rate of 115200 is not possible. To address this problem, the part has added a dedicated baud rate timer (Timer 3) specifically for generating highly accurate baud rates.
ADuC841/ADuC842/ADuC843 Table 34. Commonly Used Baud Rates Using Timer 3 with the 16.777216 MHz PLL Clock Ideal Baud 230400 CD 0 DIV 2 T3CON 82H T3FD 09H % Error 0.25 115200 115200 115200 0 1 2 3 2 1 83H 82H 81H 09H 09H 09H 0.25 0.25 0.25 57600 57600 57600 57600 0 1 2 3 4 3 2 1 84H 83H 82H 81H 09H 09H 09H 09H 0.25 0.25 0.25 0.25 38400 38400 38400 38400 0 1 2 3 4 3 2 1 84H 83H 82H 81H 2DH 2DH 2DH 2DH 0.2 0.2 0.2 0.
ADuC841/ADuC842/ADuC843 INTERRUPT SYSTEM The ADuC841/ADuC842/ADuC843 provide a total of nine interrupt sources with two priority levels. The control and configuration of the interrupt system is carried out through three interrupt-related SFRs: IE Interrupt Enable Register IP Interrupt Priority Register IEIP2 Secondary Interrupt Enable Register IE Interrupt Enable Register SFR Address A8H Power-On Default 00H Bit Addressable Yes Table 35. IE SFR Bit Designations Bit No.
ADuC841/ADuC842/ADuC843 IEIP2 SFR Address Power-On Default Bit Addressable Secondary Interrupt Enable Register A9H A0H No Table 37. IEIP2 SFR Bit Designations Bit No. Name Description 7 6 5 4 ---PTI PPSM PSI Reserved. Priority for time interval interrupt. Priority for power supply monitor interrupt. Priority for SPI/I2C interrupt. 3 2 1 0 ---ETI EPSMI ESI This bit must contain zero. Set by the user to enable, or cleared to disable time interval counter interrupts.
ADuC841/ADuC842/ADuC843 HARDWARE DESIGN CONSIDERATIONS This section outlines some of the key hardware design considerations that must be addressed when integrating the ADuC841/ADuC842/ADuC843 into any hardware system. ADuC842/ADuC843 EXTERNAL CLOCK SOURCE The clock source for the parts can be generated by the internal PLL or by an external clock input. To use the internal PLL, connect a 32.
ADuC841/ADuC842/ADuC843 DIGITAL SUPPLY If access to more than 64 kBytes of RAM is desired, a feature unique to the ADuC841/ADuC842/ADuC843 allows addressing up to 16 MBytes of external RAM simply by adding an additional latch as illustrated in Figure 79. ANALOG SUPPLY 10µF + – 10µF + – AVDD DVDD SRAM 0.1µF D0–D7 (DATA) LATCH DGND AGND 03260-0-080 P0 A0–A7 ALE Figure 80. External Dual-Supply Connections A8–A15 LATCH A16–A23 RD OE WR WE 03260-0-079 P2 Figure 79.
ADuC841/ADuC842/ADuC843 Power Consumption The currents consumed by the various sections of the part are shown in Table 40. The core values given represent the current drawn by DVDD, while the rest (ADC, DAC, voltage ref) are pulled by the AVDD pin and can be disabled in software when not in use. The other on-chip peripherals (such as the watchdog timer and the power supply monitor) consume negligible current, and are therefore lumped in with the core operating current here.
ADuC841/ADuC842/ADuC843 5 V Part For DVDD below 4.5 V, the internal POR holds the part in reset. As DVDD rises above 4.5 V, an internal timer times out for approximately 128 ms before the part is released from reset. The user must ensure that the power supply has reached a stable 4.75 V minimum level by this time. Likewise on power-down, the internal POR holds the part in reset until the power supply has dropped below 1 V. Figure 83 illustrates the operation of the internal POR in detail. 4.75V DVDD 1.
ADuC841/ADuC842/ADuC843 DOWNLOAD/DEBUG ENABLE JUMPER (NORMALLY OPEN) 1kΩ DVDD DVDD ANALOG INPUT 48 47 46 44 43 42 41 AVDD VREF OUTPUT 39 38 ADuC841/ADuC842/ADuC843 AVDD 2-PIN HEADER FOR EMULATION ACCESS (NORMALLY OPEN) 40 EA 49 45 PSEN 50 DVDD 51 52 ADC0 DGND 1kΩ 37 36 DVDD DGND 35 AGND DVDD 34 CREF XTAL2 33 VREF XTAL1 32 DAC0 31 DAC1 30 DAC OUTPUT 11.0592MHz (ADuC841) 32.
ADuC841/ADuC842/ADuC843 Note that PSEN is normally an output (as described in the External Memory Interface section) and is sampled as an input only on the falling edge of RESET, i.e., at power-up or upon an external manual reset. Note also that if any external circuitry unintentionally pulls PSEN low during power-up or reset events, it could cause the chip to enter download mode and therefore fail to begin user code execution as it should.
ADuC841/ADuC842/ADuC843 TIMING SPECIFICATIONS1, 2, 3 Table 41. AVDD =2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V; all specifications TMIN to TMAX, unless otherwise noted Parameter ADuC842/ADuC843 CLOCK INPUT (External Clock Driven XTAL1) tCK XTAL1 Period tCKL XTAL1 Width Low tCKH XTAL1 Width High tCKR XTAL1 Rise Time tCKF XTAL1 Fall Time 1/tCORE ADuC842/ADuC843 Core Clock Frequency4 tCORE ADuC842/ADuC843 Core Clock Period5 tCYC ADuC842/ADuC843 Machine Cycle Time6 32.
ADuC841/ADuC842/ADuC843 Parameter EXTERNAL DATA MEMORY READ CYCLE tRLRH RD Pulse Width tAVLL Address Valid after ALE Low tLLAX Address Hold after ALE Low tRLDV RD Low to Valid Data In tRHDX Data and Address Hold after RD tRHDZ Data Float after RD tLLDV ALE Low to Valid Data In tAVDV Address to Valid Data In tLLWL ALE Low to RD or WR Low tAVWL Address Valid to RD or WR Low tRLAZ RD Low to Address Float tWHLH RD or WR High to ALE High Min 60 60 145 16 MHz Core Clk Max Min 125 120 290 8 MHz Core Clock Max
ADuC841/ADuC842/ADuC843 Parameter EXTERNAL DATA MEMORY WRITE CYCLE tWLWH WR Pulse Width tAVLL Address Valid after ALE Low tLLAX Address Hold after ALE Low tLLWL ALE Low to RD or WR Low tAVWL Address Valid to RD or WR Low tQVWX Data Valid to WR Transition tQVWH Data Setup before WR tWHQX Data and Address Hold after WR tWHLH RD or WR High to ALE High Min 65 60 65 16 MHz Core Clk Max Min 130 120 135 130 190 60 120 380 60 8 MHz Core Clock Max 260 375 120 250 755 125 ALE (O) tWHLH PSEN (O) t LLWL t WL
ADuC841/ADuC842/ADuC843 Parameter I2C COMPATIBLE INTERFACE TIMING tL SCLOCK Low Pulse Width tH SCLOCK High Pulse Width tSHD Start Condition Hold Time tDSU Data Setup Time tDHD Data Hold Time tRSU Setup Time for Repeated Start tPSU Stop Condition Setup Time tBUF Bus Free Time between a Stop Conditionand a Start Condition tR Rise Time of Both SCLOCK and SDATA tF Fall Time of Both SCLOCK and SDATA tSUP1 Pulse Width of Spike Suppressed Min 1.3 0.6 0.6 100 Max Unit µs µs µs µs µs µs µs µs ns ns ns 0.9 0.6 0.
ADuC841/ADuC842/ADuC843 Parameter SPI MASTER MODE TIMING (CPHA = 1) tSL SCLOCK Low Pulse Width1 tSH SCLOCK High Pulse Width1 tDAV Data Output Valid after SCLOCK Edge tDSU Data Input Setup Time before SCLOCK Edge tDHD Data Input Hold Time after SCLOCK Edge tDF Data Output Fall Time tDR Data Output Rise Time tSR SCLOCK Rise Time tSF SCLOCK Fall Time Typ 476 476 Max 50 100 100 10 10 10 10 25 25 25 25 Characterized under the following conditions: a.
ADuC841/ADuC842/ADuC843 Parameter SPI MASTER MODE TIMING (CPHA = 0) tSL SCLOCK Low Pulse Width1 tSH SCLOCK High Pulse Width1 tDAV Data Output Valid after SCLOCK Edge tDOSU Data Output Setup before SCLOCK Edge tDSU Data Input Setup Time before SCLOCK Edge tDHD Data Input Hold Time after SCLOCK Edge tDF Data Output Fall Time tDR Data Output Rise Time tSR SCLOCK Rise Time tSF SCLOCK Fall Time Typ 476 476 Max 50 150 100 100 10 10 10 10 25 25 25 25 Characterized under the following conditions: a.
ADuC841/ADuC842/ADuC843 Parameter SPI SLAVE MODE TIMING (CPHA = 1) tSS SS to SCLOCK Edge tSL SCLOCK Low Pulse Width tSH SCLOCK High Pulse Width tDAV Data Output Valid after SCLOCK Edge tDSU Data Input Setup Time before SCLOCK Edge tDHD Data Input Hold Time after SCLOCK Edge tDF Data Output Fall Time tDR Data Output Rise Time tSR SCLOCK Rise Time tSF SCLOCK Fall Time tSFS SS High after SCLOCK Edge Min 0 Typ Max 330 330 50 100 100 10 10 10 10 25 25 25 25 0 SS tSFS tSS SCLOCK (CPOL = 0) tSH tSL tSR
ADuC841/ADuC842/ADuC843 Parameter SPI SLAVE MODE TIMING (CPHA = 0) tSS SS to SCLOCK Edge tSL SCLOCK Low Pulse Width tSH SCLOCK High Pulse Width tDAV Data Output Valid after SCLOCK Edge tDSU Data Input Setup Time before SCLOCK Edge tDHD Data Input Hold Time after SCLOCK Edge tDF Data Output Fall Time tDR Data Output Rise Time tSR SCLOCK Rise Time tSF SCLOCK Fall Time tDOSS Data Output Valid after SS Edge tSFS SS High after SCLOCK Edge Min 0 Typ Max 330 330 50 100 100 10 10 10 10 25 25 25 25 20 SS tSFS
ADuC841/ADuC842/ADuC843 OUTLINE DIMENSIONS 1.03 0.88 0.73 14.15 13.90 SQ 13.65 2.45 MAX 39 27 40 SEATING PLANE 26 7.80 REF 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) VIEW A PIN 1 14 52 2.10 2.00 1.95 1 7° 0° 0.13 MIN COPLANARITY VIEW A 0.23 0.11 13 0.65 BSC 0.38 0.22 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MO-112-AC-1 Figure 95. 52-Lead Plastic Quad Flatpack [MQFP] (S-52) Dimensions shown in millimeters 8.00 BSC SQ 0.60 MAX 0.60 MAX 43 42 PIN 1 INDICATOR 7.
ADuC841/ADuC842/ADuC843 ORDERING GUIDES Table 42.
ADuC841/ADuC842/ADuC843 Notes Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03260-0-11/03(0) Rev.