Datasheet

ManualsBrandsANALOG DEVICES ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller MQFP 52 (10x10) 8-Bit 12.58 MHz I/O number 34

MicroConverter

Multichannel

24-/16-Bit ADCs with Embedded 62 kB

Flash and Single-Cycle MCU

Data Sheet

ADuC845/ADuC847/ADuC848

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FEATURES

High resolution Σ-Δ ADCs

2 independent 24-bit ADCs on the ADuC845

Single 24-bit ADC on the ADuC847 and

single 16-bit ADC on the ADuC848

Up to 10 ADC input channels on all parts

24-bit no missing codes

22-bit rms (19.5 bit p-p) effective resolution

Offset drift 10 nV/°C, gain drift 0.5 ppm/°C chop enabled

Memory

62-kbyte on-chip Flash/EE program memory

4-kbyte on-chip Flash/EE data memory

Flash/EE, 100-year retention, 100 kcycle endurance

3 levels of Flash/EE program memory security

In-circuit serial download (no external hardware)

High speed user download (5 sec)

2304 bytes on-chip data RAM

8051-based core

8051-compatible instruction set

High performance single-cycle core

32 kHz external crystal

On-chip programmable PLL (12.58 MHz max)

3 × 16-bit timer/counter

24 programmable I/O lines, plus 8 analog or

digital input lines

11 interrupt sources, two priority levels

Dual data pointer, extended 11-bit stack pointer

On-chip peripherals

Internal power-on reset circuit

12-bit voltage output DAC

Dual 16-bit Σ-Δ DACs

On-chip temperature sensor (ADuC845 only)

Dual excitation current sources (200 µA)

Time interval counter (wake-up/RTC timer)

UART, SPI®, and I

C® serial I/O

High speed dedicated baud rate generator (incl. 115,200)

Watchdog timer (WDT)

Power supply monitor (PSM)

Power

Normal: 4.8 mA max @ 3.6 V (core CLK = 1.57 MHz)

Power-down: 20 µA max with wake-up timer running

Specified for 3 V and 5 V operation

Package and temperature range:

52-lead MQFP (14 mm × 14 mm), −40°C to +125°C

56-le

ad LFCSP (8 mm × 8 mm), −40°C to +85°C

APPLICATIONS

Multichannel sensor monitoring

Industrial/environmental instrumentation

Weigh scales, pressure sensors, temperature monitoring

Portable instrumentation, battery-powered systems

Data logging, precision system monitoring

FUNCTIONAL BLOCK DIAGRAM

62 kBYTES FLASH/EE PROGRAM MEMORY

4 kBYTES FLASH/EE DATA MEMORY

2304 BYTES USER RAM

3 × 16 BIT TIMERS

BAUD RATE TIMER

4 × PARALLEL

PORTS

SINGLE-CYCLE 8061-BASED MCU

ADuC845

TEMP

SENSOR

CURRENT

SOURCE

AIN1

AIN10

AINCOM

RESET

DGND

WAKE-UP/

RTC TIMER

IEXC1

IEXC2

PWM0

PGA

BUF

MUX

AUXILIARY

24-BIT S-D ADC

PRIMARY

24-BIT S-D ADC

DAC

BUF

PWM1

12-BIT

DAC

DUAL 16-BIT

S-D DAC

DUAL 16-BIT

PWM

POWER SUPPLY MON

WATCHDOG TIMER

UART, SPI, AND I

SERIAL I/O

MUX

04741-001

XTAL2XTAL1

OSC

AVCO

AGND

PLL AND PRG

CLOCK DIV

POR

REFIN+

REFIN–

REFIN2–

REFIN2+

EXTERNAL

REF

DETECT

INTERNAL

BAND GAP

REF

Figure 1. ADuC845 Functional Block Diagram

Summary of content (108 pages)

PAGE 1
MicroConverter® Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU ADuC845/ADuC847/ADuC848 Data Sheet FEATURES High resolution Σ-Δ ADCs 2 independent 24-bit ADCs on the ADuC845 Single 24-bit ADC on the ADuC847 and single 16-bit ADC on the ADuC848 Up to 10 ADC input channels on all parts 24-bit no missing codes 22-bit rms (19.5 bit p-p) effective resolution Offset drift 10 nV/°C, gain drift 0.
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ADuC845/ADuC847/ADuC848 Data Sheet TABLE OF CONTENTS Specifications..................................................................................... 4 ADC SFR Interface..................................................................... 39 Abosolute Maximum Ratings ....................................................... 10 ADCSTAT (ADC Status Register) ........................................... 40 ESD Caution ................................................................................
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Data Sheet ADuC845/ADuC847/ADuC848 Power-On Reset Operation........................................................88 QuickStart-PLUS Development System .................................. 94 Power Consumption ...................................................................88 Timing Specifications ..................................................................... 95 Power-Saving Modes ..................................................................88 Outline Dimensions ........................
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ADuC845/ADuC847/ADuC848 Data Sheet SPECIFICATIONS1 AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) = 2.5 V, REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz crystal; all specifications TMIN to TMAX, unless otherwise noted. Input buffer on for primary ADC, unless otherwise noted. Core speed = 1.57 MHz (default CD = 3), unless otherwise noted. Table 1. Parameter PRIMARY ADC Conversion Rate Unit Conditions Hz Hz Bits Bits Chop on (ADCMODE.
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Data Sheet Parameter ADuC845/ADuC847/ADuC848 Min Typ Max Unit Conditions 75 dB 100 67 dB dB dB nA nA pA/°C pA/°C nA/V pA/V/°C V 50 Hz/60 Hz ± 1 Hz, 16.6 Hz Fadc, SF = 52H, chop on, REJ60 on 50 Hz ± 1 Hz, 16.6 Hz Fadc, SF = 52H, chop on 50 Hz/60 Hz ± 1 Hz, 50 Hz Fadc, SF = 52H, chop off, REJ60 on 50 Hz ± 1 Hz, 50 Hz Fadc, SF = 52H, chop off TMAX = 85°C, buffer on TMAX = 125°C, buffer on TMAX = 85°C, buffer on TMAX = 125°C, buffer on ±2.
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ADuC845/ADuC847/ADuC848 Parameter AUXILIARY ADC ANALOG INPUTS (ADuC845 Only) Differential Input Voltage Ranges5, 6 Bipolar Mode (ADC1CON.5 = 0) Unipolar Mode (ADC1CON.5 = 1) Average Analog Input Current Analog Input Current Drift Absolute AIN/AINCOM Voltage Limits2, 7 Min Data Sheet Typ Max Unit Conditions V V nA/V pA/V/°C V REFIN = REFIN(+) − REFIN(−) (or Int 1.25 VREF) REFIN = REFIN(+) − REFIN(−) (or Int 1.25 VREF) 75 dB 100 67 dB dB 100 dB 50 Hz/60 Hz ± 1 Hz, 16.
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Data Sheet Parameter TRANSDUCER BURNOUT CURRENT SOURCES AIN+ Current ADuC845/ADuC847/ADuC848 Min AIN− Current Initial Tolerance at 25°C Drift EXCITATION CURRENT SOURCES Output Current Initial Tolerance at 25°C Drift Initial Current Matching at 25°C Drift Matching Line Regulation (AVDD) Load Regulation Output Compliance2 POWER SUPPLY MONITOR (PSM) AVDD Trip Point Selection Range AVDD Trip Point Accuracy DVDD Trip Point Selection Range DVDD Trip Point Accuracy Typ Unit Conditions −100 nA 100 nA AIN+
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ADuC845/ADuC847/ADuC848 Parameter LOGIC OUTPUTS (All Digital Outputs except XTAL2) VOH, Output High Voltage2 Min Data Sheet Typ Unit Conditions DVDD = 5 V, ISOURCE = 80 µA DVDD = 3 V, ISOURCE = 20 µA ISINK = 8 mA, SCLOCK, SDATA ISINK = 1.6 mA on P0, P1, P2 10 V V V V µA pF 600 3 2 ms ms ms 20 20 20 µs µs µs 30 30 µs µs 2.4 2.4 VOL, Output Low Voltage 0.4 0.
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Data Sheet Parameter PWM −Fxtal −Fvco TIC 3 V Power Consumption Normal Mode11, 12 DVDD Current ADuC845/ADuC847/ADuC848 Min Typ Max 3 0.5 1 Conditions µA mA µA 2.7 V < DVDD < 3.6 V, AVDD = 3.6 V 9 AVDD Current Power-Down Mode11, 12 DVDD Current Unit 20 29 14 21 4.8 11 180 mA mA µA Core clock = 1.57 MHz Core clock = 6.
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ADuC845/ADuC847/ADuC848 Data Sheet ABOSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 2.
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Data Sheet ADuC845/ADuC847/ADuC848 P0.1/AD1 P0.0/AD0 ALE PSEN 46 45 44 43 EA P0.2/AD2 52 47 53 48 P0.5/AD5 P0.4/AD4 DVDD 54 DGND P0.3/AD3 P0.6/AD6 55 50 P1.0/AIN1 P0.7/AD7 56 EA ALE PSEN P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 DVDD DGND P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS P1.1/AIN2 P1.2/AIN3/REFIN2+ 1 38 P2.6/PWM1 2 42 41 P1.2/AIN3/REFIN2+ 3 37 P2.5/PWM0 P1.3/AIN4/REFIN2– 3 40 P2.5/PWM0 P1.
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ADuC845/ADuC847/ADuC848 Data Sheet Pin No: 52-MQFP 9 Pin No: 56-LFCSP 9 Mnemonic P1.4/AIN5 Type 1 I 10 10 P1.5/AIN6 I 11 11 P1.6/AIN7/IEXC1 I/O 12 12 P1.7/AIN8/IEXC2 I/O 13 13 AINCOM/DAC I/O 14 ---- 14 15 DAC AIN9 O I ---- 16 AIN10 I 15 17 RESET I 16–19 22–25 18–21 24–27 P3.0–P3.7 I/O 16 17 18 19 22 23 24 18 19 20 21 24 25 26 P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR 25 27 P3.7/RD Description On power-on default, P1.
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Data Sheet Pin No: 52-MQFP 20, 34, 48 21, 35, 47 26 Pin No: 56-LFCSP ADuC845/ADuC847/ADuC848 28 Mnemonic DVDD DGND SCLK (I2C) Type 1 S S I/O 27 29 SDATA I/O 28–31, 36–39 30–33, 39– 42 P2.0–P2.7 I/O 28 30 P2.0/SCLOCK (SPI) 29 31 P2.1/MOSI 30 32 P2.2/MISO 31 33 P2.3/SS/T2 36 39 P2.4/T2EX 37 38 39 32 33 40 41 42 34 35 P2.5/PWM0 P2.6/PWM1 P2.7/PWMCLK XTAL1 XTAL2 40 43 EA 41 44 PSEN O 42 45 ALE O 22, 36, 51 23, 37, 38, 50 I O Description Digital Supply Voltage.
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ADuC845/ADuC847/ADuC848 Pin No: 52-MQFP 43–46, 49–52 1 Pin No: 56-LFCSP 46–49, 52– 55 Mnemonic P0.0–P0.7 EP EPAD Data Sheet Type 1 I/O Description These pins are part of Port 0, which is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and, in that state, can be used as high impedance inputs. An external pull-up resistor is required on P0 outputs to force a valid logic high level externally.
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Data Sheet ADuC845/ADuC847/ADuC848 GENERAL DESCRIPTION The ADuC845, ADuC847, and ADuC848 are single-cycle, 12.58 MIPs, 8052 core upgrades to the ADuC834 and ADuC836. They include additional analog inputs for applications requiring more ADC channels. The ADuC845, ADuC847, and ADuC848 are complete smart transducer front ends. The family integrates high resolution Σ-Δ ADCs with flexible, up to 10-channel, input multiplexing, a fast 8-bit MCU, and program and data Flash/EE memory on a single chip.
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P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) P1.0/AIN1 P1.1/AIN2 P1.2/AIN3/REFIN2+ P1.3/AIN4/REFIN2– P1.4/AIN5 P1.5/AIN6 P1.6/AIN7/IEXC1 P1.7/AIN8/IEXC2 P2.0/SCLK (A8/A16) P2.1/MOSI (A9/A17) P2.2/MISO (A10/A18) P2.3/SS/T2 (A11/A19) P2.4/T2EX (A12/A20) P2.5/PWM0 (A13/A21) P2.6/PWM1 (A14/A22) P2.7/PWMCLK (A15/A23) P3.0 (RxD) P3.1 (TxD) P3.2 (INT0) P3.3 (INT1) P3.4 (T0) P3.5 (T1) P3.6 (WR) P3.7 (RD) Data Sheet P0.
PAGE 17
P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) P1.0/AIN1 P1.1/AIN2 P1.2/AIN3/REFIN2+ P1.3/AIN4/REFIN2– P1.4/AIN5 P1.5/AIN6 P1.6/AIN7/IEXC1 P1.7/AIN8/IEXC2 P2.0/SCLK (A8/A16) P2.1/MOSI (A9/A17) P2.2/MISO (A10/A18) P2.3/SS/T2 (A11/A19) P2.4/T2EX (A12/A20) P2.5/PWM0 (A13/A21) P2.6/PWM1 (A14/A22) P2.7/PWMCLK (A15/A23) P3.0 (RxD) P3.1 (TxD) P3.2 (INT0) P3.3 (INT1) P3.4 (T0) P3.5 (T1) P3.6 (WR) P3.7 (RD) ADuC845/ADuC847/ADuC848 P0.
PAGE 18
P2.6/PWM1 (A14/A22) P2.7/PWMCLK (A15/A23) P3.0 (RxD) P3.1 (TxD) P3.2 (INT0) P3.3 (INT1) P3.4 (T0) P3.5 (T1) P3.6 (WR) P3.7 (RD) 3 P2.5/PWM0 (A13/A21) 2 P2.4/T2EX (A12/A20) 1 P2.3/SS/T2 (A11/A19) 56 P2.2/MISO (A10/A18) P1.1/AIN2 55 P2.1/MOSI (A9/A17) P1.0/AIN1 54 P2.0/SCLK (A8/A16) P0.7 (AD7) 53 P1.6/AIN7/IEXC1 P0.6 (AD6) 52 P1.7/AIN8/IEXC2 P0.5 (AD5) 49 P1.4/AIN5 P0.4 (AD4) 48 P1.5/AIN6 P0.3 (AD3) 47 P1.2/AIN3/REFIN2+ P0.2 (AD2) 46 P1.3/AIN4/REFIN2– P0.
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Data Sheet ADuC845/ADuC847/ADuC848 COMPLETE SFR MAP WCOL SPE SPIM CPOL CPHA SPR1 SPR0 0 FEH 0 FDH 0 FCH 0 FBH 0 FAH 1 F9H 0 F8H 0 F7H 0 F6H 0 F5H 0 F4H 0 F3H 0 F2H 0 F1H 0 F0H 0 MDO EFH E7H 0 EEH D7H CFH RD B7H EA AFH A7H 0 CEH SM0 9FH 0 BEH 1 B5H EADC 0 C4H PS 0 BCH 0 AEH 0 ADH 1 SM1 0 9EH T0 1 B4H ET2 A5H ES 0 0 9DH ACH 1 A4H SM2 RS0 0 D3H TCLK PRE0 T1 1 B6H REN 0 9CH OV EXEN2 0 CBH 0 BBH 0 ABH 1 A3H CNT2 WDE PT0 0 AAH 0 9AH TF1 1 96H
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ADuC845/ADuC847/ADuC848 Data Sheet FUNCTIONAL DESCRIPTION 8051 INSTRUCTION SET Table 4.
PAGE 21
Data Sheet Mnemonic RLC A RR A RRC A Data Transfer MOV A,Rn MOV A,@Ri MOV Rn,A MOV @Ri,A MOV A,dir MOV A,#data MOV Rn,#data MOV dir,A MOV Rn, dir MOV dir, Rn MOV @Ri,#data MOV dir,@Ri MOV @Ri,dir MOV dir,dir MOV dir,#data MOV DPTR,#data MOVC A,@A+DPTR MOVC A,@A+PC MOVX 2 A,@Ri MOVX2 A,@DPTR MOVX2 @Ri,A MOVX2 @DPTR,A PUSH dir POP dir XCH A,Rn XCH A,@Ri XCHD A,@Ri XCH A,dir Boolean CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C,bit ANL C,/bit ORL C,bit ORL C,/bit MOV C,bit MOV bit,C Branching JMP @A+DPTR R
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ADuC845/ADuC847/ADuC848 Mnemonic SJMP rel JC rel JNC rel JZ rel JNZ rel DJNZ Rn,rel LJMP LCALL 3 addr16 JB bit,rel JNB bit,rel JBC bit,rel CJNE A,dir,rel CJNE A,#data,rel CJNE Rn,#data,rel CJNE @Ri,#data,rel DJNZ dir,rel Miscellaneous NOP Data Sheet Description Short jump (relative address) Jump on carry = 1 Jump on carry = 0 Jump on accumulator = 0 Jump on accumulator ! = 0 Decrement register, JNZ relative Long jump unconditional Long jump to subroutine Jump on direct bit = 1 Jump on direct bit = 0 Jump o
PAGE 23
Data Sheet ADuC845/ADuC847/ADuC848 7FH is possible (by setting CFG845.7/ADuC847.7/ADuC848.7) to enable the 11-bit extended stack pointer. In this case, the stack rolls over from FFH in RAM to 0100H in XRAM. GENERAL-PURPOSE AREA 30H 2FH The 11-bit stack pointer is visible in the SPH and SP SFRs. The SP SFR is located at 81H as with a standard 8052. The SPH SFR is located at B7H.
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ADuC845/ADuC847/ADuC848 Data Sheet Data Pointer (DPTR) SPECIAL FUNCTION REGISTERS (SFRs) The SFR space is mapped into the upper 128 bytes of internal data memory space and accessed by direct addressing only. It provides an interface between the CPU and all on-chip peripherals. A block diagram showing the programming model of the ADuC845/ADuC847/ADuC848 via the SFR area is shown in Figure 11. All registers except the program counter (PC) and the four general-purpose register banks reside in the SFR area.
PAGE 25
Data Sheet ADuC845/ADuC847/ADuC848 ADuC845/ADuC847/ADuC848 Configuration Register (CFG845/CFG847/CFG848) Power Control Register (PCON) The PCON SFR contains bits for power-saving options and general-purpose status flags as listed in Table 6. SFR Address: Power-On Default: Bit Addressable: The CFG845/CFG847/CFG848 SFR contains the bits necessary to configure the internal XRAM and the extended SP. By default, it configures the user into 8051 mode, that is, extended SP, and the internal XRAM are disabled.
PAGE 26
ADuC845/ADuC847/ADuC848 Data Sheet ADC CIRCUIT INFORMATION The ADuC845 incorporates two 10-channel (8-channel on the MQFP package) 24-bit Σ-∆ ADCs, while the ADuC847 and ADuC848 each incorporate a single 10-channel (8-channel on the MQFP package) 24-bit and 16-bit Σ-∆ ADC. Each part also includes an on-chip programmable gain amplifier and configurable buffering (neither is available on the auxiliary ADC on the ADuC845).
PAGE 27
Data Sheet ADuC845/ADuC847/ADuC848 Signal Chain Overview (Chop Enabled, CHOP = 0) With chop enabled, the ADC repeatedly reverses its inputs. The decimated digital output words from the Sinc3 filter, therefore, have a positive offset and a negative offset term included. As a result, a final summing stage is included so that each output word from the filter is summed and averaged with the previous filter output to produce a new valid output result to be written to the ADC data register.
PAGE 28
ADuC845/ADuC847/ADuC848 Data Sheet This offset is removed by performing a running average of 2. This average by 2 means that the settling time to any change in programming of the ADC is twice the normal conversion time, while an asynchronous step change on the analog input is not fully reflected until the third subsequent output. See Figure 13. 2  2  t ADC f ADC SYNCHRONOUS CHANGE (I.E.
PAGE 29
Data Sheet ADuC845/ADuC847/ADuC848 ADC Noise Performance with Chop Enabled (CHOP = 0) used in the implementation of the modulator. The second source is quantization noise, which is added when the analog input is converted to the digital domain. The device noise is at a low level and is independent of frequency. The quantization noise starts at an even lower level but rises rapidly with increasing frequency to become the dominant noise source.
PAGE 30
ADuC845/ADuC847/ADuC848 Data Sheet Signal Chain Overview with Chop Disabled (CHOP = 1) The settling time to a step input is governed by the digital filter. A synchronized step change requires a settling time of three times the programmed update rate; a channel change can be treated as a synchronized step change. This is one conversion longer than the case for chop enabled.
PAGE 31
Data Sheet ADuC845/ADuC847/ADuC848 ADC Noise Performance with Chop Disabled (CHOP = 1) Table 14, Table 15, Table 16, and Table 17 show the output rms noise and output peak-to-peak resolution in bits (rounded to the nearest 0.5 LSB) for some typical output update rates. The numbers are typical and are generated at a differential input voltage of 0 V and a common-mode voltage of 2.5 V. The output update rate is selected via the SF7 to SF0 bits in the SF filter register.
PAGE 32
ADuC845/ADuC847/ADuC848 Data Sheet When an external reference voltage is used, the primary ADC sees this internally as a 2.56 V reference (VREF × 1.024). Therefore, any calculations of LSB size should account for this. For instance, with a 2.5 V external reference connected and using a gain of 1 on a unipolar range (2.56 V), the LSB size is (2.56/224) = 152.6 nV (if using the 24-bit ADC on the ADuC845 or ADuC847). If a bipolar gain of 4 is used (±640 mV), the LSB size is (±640 mV)/224) = 76.
PAGE 33
Data Sheet ADuC845/ADuC847/ADuC848 REFERENCE DETECT CIRCUIT The main and auxiliary (ADuC845 only) ADCs can be configured to allow the use of the internal band gap reference or an external reference that is applied to the REFIN± pins by means of the XREF0/1 bit in the Control Registers AD0CON2 and AD1CON (ADuC845 only). A reference detection circuit is provided to detect whether a valid voltage is applied to the REFIN± pins.
PAGE 34
ADuC845/ADuC847/ADuC848 Data Sheet enabled for any SF word that yields an ADC throughput that is less than 20 Hz with chop enabled (SF ≥ 68 decimal). ADC CHOPPING The ADCs on the ADuC845/ADuC847/ADuC848 implement a chopping scheme whereby the ADC repeatedly reverses its inputs. The decimated digital output words from the Sinc3 filter, therefore, have a positive and negative offset term included.
PAGE 35
Data Sheet ADuC845/ADuC847/ADuC848 The primary ADC incorporates an on-chip programmable gain amplifier (PGA). The PGA can be programmed through eight different ranges, which are programmed via the range bits (RN0 to RN2) in the ADC0CON1 register. With an external 2.5 V reference applied, the unipolar ranges are 0 mV to 20 mV, 0 mV to 40 mV, 0 mV to 80 mV, 0 mV to 160 mV, 0 mV to 320 mV, 0 mV to 640 mV, 0 V to 1.28 V and 0 V to 2.
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ADuC845/ADuC847/ADuC848 Data Sheet DATA OUTPUT CODING EXCITATION CURRENTS When the primary ADC is configured for unipolar operation, the output coding is natural (straight) binary with a zero differential input voltage resulting in a code of 000...000, a midscale voltage resulting in a code of 100...000, and a full-scale voltage resulting in a code of 111...111.
PAGE 37
Data Sheet ADuC845/ADuC847/ADuC848 0 –10 –20 –20 –30 –30 –40 –40 –50 –60 –70 –50 –60 –70 –80 –80 –90 –90 –100 –100 –110 –110 –120 0 10 20 30 40 50 60 70 FREQUENCY (Hz) 80 90 100 110 –120 10 Figure 18. Filter Response, Chop On, SF = 69 Decimal 30 50 70 90 110 130 150 170 190 210 230 250 SF (Decimal) 04741-021 GAIN (dB) 0 –10 04741-018 GAIN (dB) TYPICAL PERFORMANCE CHARACTERISTICS Figure 21. 60 Hz Normal Mode Rejection vs.
PAGE 38
Data Sheet 0 –20 –20 –40 –40 –120 04741-024 –120 95 100 –100 50 55 60 65 70 75 80 85 90 –100 FREQUENCY (Hz) FREQUENCY (Hz) Figure 24. Chop On, Fadc = 16.6 Hz, SF = 52H Figure 25. Chop On, Fadc = 16.6 Hz, SF = 52H, REJ60 Enabled Rev.
PAGE 39
Data Sheet ADuC845/ADuC847/ADuC848 FUNCTIONAL DESCRIPTION ADC SFR INTERFACE The ADCs are controlled and configured via a number of SFRs that are mentioned here and described in more detail in the following sections. Table 22. ADC SFR Interface Name ADCSTAT ADCMODE ADC0CON1 ADC0CON2 ADC1CON SF ICON ADC0L/M/H ADC1L/M/H OF0L/M/H OF1L/H GN0L/M/H GN1L/H Description ADC Status Register. Holds the general status of the primary and auxiliary (ADuC845 only) ADCs. ADC Mode Register.
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ADuC845/ADuC847/ADuC848 Data Sheet ADCSTAT (ADC STATUS REGISTER) This SFR reflects the status of both ADCs including data ready, calibration, and various (ADC-related) error and warning conditions including REFIN± reference detect and conversion overflow/underflow flags. SFR Address: Power-On Default: Bit Addressable: D8H 00H Yes Table 23. ADCSTAT SFR Bit Designation Bit No. 7 Name RDY0 6 RDY1 5 CAL 4 NOXREF 3 ERR0 2 1 0 ERR1 ––– ––– Description Ready Bit for the Primary ADC.
PAGE 41
Data Sheet ADuC845/ADuC847/ADuC848 ADCMODE (ADC MODE REGISTER) Used to control the operational mode of both ADCs. SFR Address: Power-On Default: Bit Addressable: D1H 08H No Table 24. ADCMODE SFR Bit Designations Bit No. 7 6 Name ––– REJ60 5 ADC0EN 4 ADC1EN (ADuC845 only) 3 CHOP 2, 1, 0 MD2, MD1, MD0 Description Not Implemented. Write Don’t Care. Automatic 60 Hz Notch Select Bit.
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ADuC845/ADuC847/ADuC848 Data Sheet Notes on the ADCMODE Register • Any change to the MD bits immediately resets both ADCs (auxiliary ADC only applicable to the ADuC845). A write to the MD2–MD0 bits with no change in contents is also treated as a reset. (See the exception to this in the third note of this section.) • If the parts are powered down via the PD bit in the PCON register, the current ADCMODE bits are preserved, that is, they are not reset to default state.
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Data Sheet ADuC845/ADuC847/ADuC848 ADC0CON1 (PRIMARY ADC CONTROL REGISTER) ADC0CON1 is used to configure the primary ADC for buffer, unipolar, or bipolar coding, and ADC range configuration. SFR Address: Power-On Default: Bit Addressable: D2H 07H No Table 25. ADC0CON1 SFR Bit Designations Bit No. 7, 6 Name BUF1, BUF0 5 UNI 4 3 2, 1, 0 ––– ––– RN2, RN1, RN0 Description Buffer Configuration Bits.
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ADuC845/ADuC847/ADuC848 Data Sheet ADC0CON2 (PRIMARY ADC CHANNEL SELECT REGISTER) ADC0CON2 is used to select a reference source and channel for the primary ADC. SFR Address: Power-On Default: Bit Addressable: E6H 00H No Table 26. ADC0CON2 SFR Bit Designations Bit No. 7, 6 Name XREF1, XREF0 5 4 3, 2, 1, 0 ––– ––– CH3, CH2, CH1, CH0 Description Primary ADC External Reference Select Bit. Set by the user to enable the primary ADC to use the external reference via REFIN± or REFIN2±.
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Data Sheet ADuC845/ADuC847/ADuC848 ADC1CON (AUXILIARY ADC CONTROL REGISTER) (ADuC845 ONLY) ADC1CON is used to configure the auxiliary ADC for reference, channel selection, and unipolar or bipolar coding. The auxiliary ADC is available only on the ADuC845. SFR Address: Power-On Default: Bit Addressable: D3H 00H No Table 27. ADC1CON SFR Bit Designations Bit No. 7 6 Name ––– AXREF 5 AUNI 4 3, 2, 1, 0 ––– ACH3, ACH2, ACH1, ACH0 1 Description Not Implemented. Write Don’t Care.
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ADuC845/ADuC847/ADuC848 Data Sheet SF (ADC SINC FILTER CONTROL REGISTER) The SF register is used to configure the decimation factor for the ADC, and therefore, has a direct influence on the ADC throughput rate. SFR Address: Power-On Default: Bit Addressable: D4H 45H No Table 28. Sinc Filter SFR Bit Designations SF.7 0 SF.6 1 SF.5 0 SF.4 0 SF.3 0 SF.2 1 SF.1 0 SF.0 1 The bits in this register set the decimation factor of the ADC.
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Data Sheet ADuC845/ADuC847/ADuC848 ICON (EXCITATION CURRENT SOURCES CONTROL REGISTER) The ICON register is used to configure the current sources and the burnout detection source. SFR Address: Power-On Default: Bit Addressable: D5H 00H No Table 30. Excitation Current Source SFR Bit Designations Bit No. 7 6 Name ––– ICON.6 5 4 3 2 1 0 ICON.5 ICON.4 ICON.3 ICON.2 ICON.1 ICON.0 Description Not Implemented. Write Don’t Care. Burnout Current Enable Bit.
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ADuC845/ADuC847/ADuC848 Data Sheet NONVOLATILE FLASH/EE MEMORY OVERVIEW The ADuC845/ADuC847/ADuC848 incorporate Flash/EE memory technology on-chip to provide the user with nonvolatile, in-circuit reprogrammable code and data memory space. Like EEPROM, flash memory can be programmed in-system at the byte level, although it must first be erased, in page blocks. Thus, flash memory is often and more correctly referred to as Flash/EE memory.
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Data Sheet ADuC845/ADuC847/ADuC848 Serial Downloading (In-Circuit Programming) 300 The ADuC845/ADuC847/ADuC848 facilitate code download via the standard UART serial port. The parts enter serial download mode after a reset or a power cycle if the PSEN pin is pulled low through an external 1 kΩ resistor. Once in serial download mode, the hidden embedded download kernel executes.
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ADuC845/ADuC847/ADuC848 Data Sheet USER DOWNLOAD MODE (ULOAD) However, most of the Flash/EE program memory can also be written to during run time simply by entering ULOAD mode. In ULOAD mode, the lower 56 kbytes of program memory can be erased and reprogrammed by the user software as shown in Figure 30. ULOAD mode can be used to upgrade the code in the field via any user-defined download protocol.
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BYTE 3 (0FFEH) BYTE 4 (0FFFH) 3FEH BYTE 1 (0FF8H) BYTE 2 (0FF9H) BYTE 3 (0FFAH) BYTE 4 (0FFBH) 03H BYTE 1 (000CH) BYTE 2 (000DH) BYTE 3 (000EH) BYTE 4 (000FH) 02H BYTE 1 (0008H) BYTE 2 (0009H) BYTE 3 (000AH) BYTE 4 (000BH) 01H BYTE 1 (0004H) BYTE 2 (0005H) BYTE 3 (0006H) BYTE 4 (0007H) 00H BYTE 1 (0000H) BYTE 2 (0001H) BYTE 3 (0002H) BYTE 4 (0003H) BYTE ADDRESSES ARE GIVEN IN BRACKETS Programming either Flash/EE data memory or Flash/EE program memory is done through the Flash/EE
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ADuC845/ADuC847/ADuC848 Data Sheet Example: Programming the Flash/EE Data Memory A user wants to program F3H into the second byte on Page 03H of the Flash/EE data memory space while preserving the other 3 bytes already in this page. A typical program of the Flash/EE data array involves 1. Setting EADRH/L with the page address. 2. Writing the data to be programmed to the EDATA1–4. 3. Writing the ECON SFR with the appropriate command.
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Data Sheet ADuC845/ADuC847/ADuC848 DAC CIRCUIT INFORMATION The ADuC845/ADuC847/ADuC848 incorporate a 12-bit, voltage output DAC on-chip. It has a rail-to-rail voltage output buffer capable of driving 10 kΩ/100 pF, and has two selectable ranges, 0 V to VREF and 0 V to AVDD. It can operate in 12-bit or 8-bit mode. The DAC has a control register, DACCON, and two data registers, DACH/L. The DAC output can be programmed to appear at Pin 14 (DAC) or Pin 13 (AINCOM).
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ADuC845/ADuC847/ADuC848 Data Sheet Using the DAC VDD The on-chip DAC architecture consists of a resistor string DAC followed by an output buffer amplifier, the functional equivalent of which is shown in Figure 33. VDD–50mV VDD–100mV AVDD VREF R OUTPUT BUFFER 100mV R 14 0mV FFFH 000H HIGH-Z DISABLE (FROM MCU) 04741-034 50mV R Figure 34. Endpoint Nonlinearities Due to Amplifier Saturation Figure 33.
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Data Sheet ADuC845/ADuC847/ADuC848 3 PULSE-WIDTH MODULATOR (PWM) The ADuC845/ADuC847/ADuC848 has a highly flexible PWM offering programmable resolution and an input clock. The PWM can be configured in six different modes of operation. Two of these modes allow the PWM to be configured as a Σ-Δ DAC with up to 16 bits of resolution. A block diagram of the PWM is shown in Figure 38. OUTPUT VOLTAGE (V) DAC LOADED WITH 0FFFH 2 1 12.583MHz (FVCO) EXTERNAL CLOCK ON P2.7 32.
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ADuC845/ADuC847/ADuC848 Data Sheet PWMCON PWM Control SFR SFR Address: Power-On Default: Bit Addressable: AEH 00H No Table 34. PWMCON PWM Control SFR Bit No. 7 6, 5, 4 Name ––– PWM2, PWM1, PWM0 3, 2 PWS1, PWS0 1, 0 PWC1, PWC0 Description Not Implemented. Write Don’t Care. PMW Mode Selection. PWM2 PWM1 PWM0 0 0 0 Mode 0: PWM disabled. 0 0 1 Mode 1: Single 16-bit output with programmable pulse and cycle time. 0 1 0 Mode 2: Twin 8-bit outputs. 0 1 1 Mode 3: Twin 16-bit outputs.
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Data Sheet ADuC845/ADuC847/ADuC848 PWM Cycle Width High Byte (PWM1H) SFR Address: Power-On Default: Bit Addressable: B4H 00H No Table 37. PWM1H: PWM Cycle Width High Byte PWM1H.7 0 R/W PWM1H.6 0 R/W PWM1H.5 0 R/W PWM1H.4 0 R/W PWM1H.3 0 R/W PWM1H.2 0 R/W PWM1H.1 0 R/W PWM1H.0 0 R/W PWM Cycle Width Low Byte (PWM1L) SFR Address: Power-On Default: Bit Addressable: B3H 00H No Table 38. PWM1L: PWM Cycle Width Low Byte PWM1L.7 PWM1L.6 PWM1L.5 PWM1L.4 PWM1L.3 PWM1L.2 PWM1L.1 PWM1L.
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ADuC845/ADuC847/ADuC848 Data Sheet Mode 3 (Twin 16-Bit PWM) Mode 4 (Dual NRZ 16-Bit Σ-∆ DAC) In Mode 3, the PWM counter is fixed to count from 0 to 65536, giving a fixed 16-bit PWM. Operating from the 12.58 MHz core clock results in a PWM output rate of 192 Hz. The duty cycle of the PWM outputs at P2.5 and P2.6 are independently programmable. Mode 4 provides a high speed PWM output similar to that of a Σ-Δ DAC. Typically, this mode is used with the PWM clock equal to 12.58 MHz.
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Data Sheet ADuC845/ADuC847/ADuC848 Mode 5 (Dual 8-Bit PWM) In Mode 5, the duty cycle and the resolution of the PWM outputs are individually programmable. The maximum resolution of the PWM output is 8 bits. PWM1L The output resolution is set by the PWM1L and PWM1H SFRs for the P2.5 and P2.6 outputs, respectively. PWM0L and PWM0H set the duty cycles of the PWM outputs at P2.5 and P2.6, respectively. Both PWMs have the same clock source and clock divider.
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ADuC845/ADuC847/ADuC848 Data Sheet ON-CHIP PLL (PLLCON) The ADuC845/ADuC847/ADuC848 are intended for use with a 32.768 kHz watch crystal. A PLL locks onto a multiple (384) of this to provide a stable 12.582912 MHz clock for the system. The core can operate at this frequency or at binary submultiples of it to allow power saving when maximum core performance is not required. The default core clock is the PLL clock divided by 8 or 1.572864 MHz.
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Data Sheet ADuC845/ADuC847/ADuC848 I2C SERIAL INTERFACE The ADuC845/ADuC847/ADuC848 support a fully licensed I2C serial interface. The I2C interface is implemented as a full hardware slave and software master. SDATA (Pin 27 on the MQFP package and Pin 29 on the LFCSP package) is the data I/O pin. SCLK (Pin 26 on the MQFP package and Pin 28 on the LFCSP package) is the serial interface clock for the SPI interface. The I2C interface on the parts is fully independent of all other pin/function multiplexing.
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ADuC845/ADuC847/ADuC848 Data Sheet I2CADD—I2C Address Register 1 Function: Holds one of the I2C peripheral addresses for the part. It may be overwritten by user code. Application Note uC001 at http://www.analog.com/microconverter describes the format of the I2C standard 7-bit address. 9BH 55H No SFR Address: Power-On Default: Bit Addressable: I2CADD1—I2C Address Register 2 Function: SFR Address: Power-On Default: Bit Addressable: Same as the I2CADD.
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Data Sheet ADuC845/ADuC847/ADuC848 Hardware Slave Mode After reset, the ADuC845/ADuC847/ADuC848 default to hardware slave mode. Slave mode is enabled by clearing the I2CM bit in I2CCON. The parts have a full hardware slave. In slave mode, the I2C address is stored in the I2CADD register. Data received or to be transmitted is stored in the I2CDAT register. Once enabled in I2C slave mode, the slave controller waits for a start condition.
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ADuC845/ADuC847/ADuC848 Data Sheet SPI SERIAL INTERFACE MISO (Master In, Slave Out Pin) The ADuC845/ADuC847/ADuC848 integrate a complete hardware serial peripheral interface (SPI) interface on-chip. SPI is an industry-standard synchronous serial interface that allows 8 bits of data to be synchronously transmitted and received simultaneously, that is, full duplex. Note that the SPI pins are multiplexed with the Port 2 pins, P2.0, P2.1, P2.2, and P2.3. These pins have SPI functionality only if SPE is set.
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Data Sheet ADuC845/ADuC847/ADuC848 SPICON—SPI Control Register SFR Address: Power-On Default: Bit Addressable: F8H 05H Yes Table 41. SPICON SFR Bit Designations Bit No. 7 Name ISPI 6 WCOL 5 SPE 4 SPIM 3 CPOL 1 2 CPHA1 1, 0 SPR1, SPR0 1 Description SPI Interrupt Bit. Set by the MicroConverter at the end of each SPI transfer. Cleared directly by user code or indirectly by reading the SPIDAT SFR. Write Collision Error Bit.
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ADuC845/ADuC847/ADuC848 Data Sheet SPI Interface—Master Mode USING THE SPI INTERFACE In master mode, the SCLOCK pin is always an output and generates a burst of eight clocks whenever user code writes to the SPIDAT register. The SCLOCK bit rate is determined by SPR0 and SPR1 in SPICON. Also note that the SS pin is not used in master mode. If the parts need to assert the SS pin on an external slave device, a port digital output pin should be used.
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Data Sheet ADuC845/ADuC847/ADuC848 DUAL DATA POINTERS DPCON—Data Pointer Control SFR The parts incorporate two data pointers. The second data pointer is a shadow data pointer and is selected via the data pointer control SFR (DPCON). DPCON features automatic hardware post-increment and post-decrement as well as an automatic data pointer toggle. SFR Address: Power-On Default: Bit Addressable: A7H 00H No Table 42. DPCON SFR Bit Designations Bit No.
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ADuC845/ADuC847/ADuC848 Data Sheet POWER SUPPLY MONITOR The power supply monitor, once enabled, monitors the DVDD and AVDD supplies on the parts. It indicates when any of the supply pins drop below one of four user-selectable voltage trip points from 2.63 V to 4.63 V. For correct operation of the power supply monitor function, AVDD must be equal to or greater than 2.63 V. Monitor function is controlled via the PSMCON SFR.
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Data Sheet ADuC845/ADuC847/ADuC848 WATCHDOG TIMER The watchdog timer generates a device reset or interrupt within a reasonable amount of time if the ADuC845/ADuC847/ ADuC848 enters an erroneous state, possibly due to a programming error or electrical noise. The watchdog function can be disabled by clearing the WDE (watchdog enable) bit in the watchdog control (WDCON) SFR.
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ADuC845/ADuC847/ADuC848 Data Sheet A TIC is provided on-chip for counting longer intervals than the standard 8051-compatible timers can count. The TIC is capable of timeout intervals ranging from 1/128 second to 255 hours. Also, this counter is clocked by the external 32.768 kHz crystal rather than by the core clock, and it can remain active in power-down mode and time long power-down intervals.
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Data Sheet ADuC845/ADuC847/ADuC848 TIMECON—TIC Control Register SFR Address: Power-On Default: Bit Addressable: A1H 00H No Table 45. TIMECON SFR Bit Designations Bit No. 7 6 Name ---TFH 5, 4 ITS1, ITS0 3 ST1 2 TII 1 TIEN 0 TCEN Description Not Implemented. Write Don’t Care. Twenty-Four Hour Select Bit. Set by the user to enable the hour counter to count from 0 to 23. Cleared by the user to enable the hour counter to count from 0 to 255. Interval Timebase Selection Bits.
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ADuC845/ADuC847/ADuC848 Data Sheet INTVAL—User Timer Interval Select Register Function: User code writes the required time interval to this register. When the 8-bit interval counter is equal to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON.2) is set and generates an interrupt, if enabled.
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Data Sheet ADuC845/ADuC847/ADuC848 This section gives a brief overview of the various secondary peripheral circuits that are available to the user on-chip. These features are mostly 8052-compatible (with a few additional features) and are controlled via standard 8052 SFR bit definitions. Parallel I/O The ADuC845/ADuC847/ADuC848 use four input/output ports to exchange data with external devices.
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ADuC845/ADuC847/ADuC848 Data Sheet DVDD P2.5 and P2.6 can also be used as PWM outputs, while P2.7 can act as an alternate PWM clock source. When selected as the PWM outputs, they overwrite anything written to P2.5 or P2.6. READ LATCH Table 47. Port 2 Alternate Functions Alternate Function SCLOCK for SPI MOSI for SPI MISO for SPI SS and T2 clock input T2EX alternate control for T2 PWM0 output PWM1 output PWMCLK ADDR CONTROL READ LATCH INTERNAL BUS WRITE TO LATCH INTERNAL BUS WRITE TO LATCH P3.
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Data Sheet ADuC845/ADuC847/ADuC848 TIMERS/COUNTERS The ADuC845/ADuC847/ADuC848 have three 16-bit timer/ counters: Timer 0, Timer 1, and Timer 2. The timer/counter hardware is included on-chip to relieve the processor core of the overhead inherent in implementing timer/counter functionality in software. Each timer/counter consists of two 8-bit registers: THx and TLx (x = 0, 1, or 2). All three can be configured to operate either as timers or as event counters.
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ADuC845/ADuC847/ADuC848 Data Sheet TCON—Timer/Counter 0 and 1 Control Register SFR Address: Power-On Default: Bit Addressable: 88H 00H Yes Table 51. TCON SFR Bit Designations Bit No. 7 Name TF1 6 TR1 5 TF0 4 TR0 3 IE11 2 IT11 1 IE01 0 IT01 Description Timer 1 Overflow Flag. Set by hardware on a Timer/Counter 1 overflow. Cleared by hardware when the program counter (PC) vectors to the interrupt service routine. Timer 1 Run Control Bit. Set by the user to turn on Timer/Counter 1.
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Data Sheet ADuC845/ADuC847/ADuC848 Timer/Counter 0 and 1 Operating Modes Mode 2 (8-Bit Timer/Counter with Autoreload) This section describes the operating modes for Timer/Counters 0 and 1. Unless otherwise noted, these modes of operation are the same for both Timer 0 and Timer 1. Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload as shown in Figure 54. Overflow from TL0 not only sets TF0, but also reloads TL0 with the contents of TH0, which is preset by software.
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ADuC845/ADuC847/ADuC848 Data Sheet T2CON—Timer/Counter 2 Control Register SFR Address: Power-On Default: Bit Addressable: C8H 00H Yes Table 52. T2CON SFR Bit Designations Bit No. 7 Name TF2 6 EXF2 5 RCLK 4 TCLK 3 EXEN2 2 TR2 1 CNT2 0 CAP2 Description Timer 2 Overflow Flag. Set by hardware on a Timer 2 overflow. TF2 cannot be set when either RCLK = 1 or TCLK = 1. Cleared by user software. Timer 2 External Flag.
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Data Sheet ADuC845/ADuC847/ADuC848 Timer/Counter 2 Operating Modes 16-Bit Capture Mode The following sections describe the operating modes for Timer/Counter 2. The operating modes are selected by bits in the T2CON SFR as shown in Table 53. Capture mode has two options that are selected by Bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter that, upon overflowing, sets bit TF2, the Timer 2 overflow bit, which can be used to generate an interrupt.
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ADuC845/ADuC847/ADuC848 Data Sheet UART SERIAL INTERFACE SBUF SFR The serial port is full duplex, meaning that it can transmit and receive simultaneously. It is also receive buffered, meaning that it can begin receiving a second byte before a previously received byte is read from the receive register. However, if the first byte is still not read by the time reception of the second byte is complete, the first byte is lost. The physical interface to the serial data network is via Pins RxD(P3.
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Data Sheet ADuC845/ADuC847/ADuC848 Mode 0 (8-Bit Shift Register Mode) Mode 0 is selected by clearing both the SM0 and SM1 bits in the SFR SCON. Serial data enters and exits through RxD. TxD outputs the shift clock. Eight data bits are transmitted or received. Transmission is initiated by any instruction that writes to SBUF. The data is shifted out of the RxD line. The 8 bits are transmitted with the least significant bit (LSB) first. DATA BIT 1 DATA BIT 6 DATA BIT 7 Figure 58.
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ADuC845/ADuC847/ADuC848 Data Sheet Mode 3 (9-Bit UART with Variable Baud Rate) The Timer 1 interrupt should be disabled in this application. The timer itself can be configured for either timer or counter operation, and in any of its three running modes. In the most typical application, it is configured for timer operation in autoreload mode (high nibble of TMOD = 0010 binary). In that case, the baud rate is given by the formula Mode 3 is selected by setting both SM0 and SM1.
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Data Sheet ADuC845/ADuC847/ADuC848 Timer 3 Generated Baud Rates The high integer dividers in a UART block mean that high speed baud rates are not always possible. Also, generating baud rates requires the exclusive use of a timer, rendering it unusable for other applications when the UART is required. To address this problem, the ADuC845/ADuC847/ADuC848 have a dedicated baud rate timer (Timer 3) specifically for generating highly accurate baud rates.
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ADuC845/ADuC847/ADuC848 Data Sheet T3FD—Timer 3 Fractional Divider Register See Table 57 for values. SFR Address: Power-On Default: Bit Addressable: 9DH 00H No Table 56. T3FD SFR Bit Designations Bit No. 7 6 5 4 3 2 1 0 Name ------T3FD.5 T3FD.4 T3FD.3 T3FD.2 T3FD.1 T3FD.0 Description Not Implemented. Write Don’t Care. Not Implemented. Write Don’t Care. Timer 3 Fractional Divider Bit 5. Timer 3 Fractional Divider Bit 4. Timer 3 Fractional Divider Bit 3. Timer 3 Fractional Divider Bit 2.
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Data Sheet ADuC845/ADuC847/ADuC848 INTERRUPT SYSTEM The ADuC845/ADuC847/ADuC848 provide nine interrupt sources with two priority levels. The control and configuration of the interrupt system is carried out through three interrupt-related SFRs: IE IP IEIP2 Interrupt Enable Register Interrupt Priority Register Secondary Interrupt Enable Register IE—Interrupt Enable Register SFR Address: Power-On Default: Bit Addressable: A8H 00H Yes Table 58. IE SFR Bit Designations Bit No.
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ADuC845/ADuC847/ADuC848 Data Sheet IEIP2—Secondary Interrupt Enable Register SFR Address: Power-On Default: Bit Addressable: A9H A0H No Table 60. IEIP2 Bit Designations Bit No. 7 6 5 4 3 2 Name ---PTI PPSM PSI ---ETI 1 EPSMI 0 ESI Description Not Implemented. Write Don’t Care. Time Interval Counter Interrupt Priority Setting (1 = High, 0 = Low). Power Supply Monitor Interrupt Priority Setting (1 = High, 0 = Low). SPI/I2C Interrupt Priority Setting (1 = High, 0 = Low). This bit must contain 0.
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Data Sheet ADuC845/ADuC847/ADuC848 HARDWARE DESIGN CONSIDERATIONS This section outlines some of the key hardware design considerations that must be addressed when integrating the ADuC845/ADuC847/ADuC848 into any hardware system. EXTERNAL MEMORY INTERFACE In addition to their internal program and data memories, the parts can access up to 16 Mbytes of external data memory (SRAM). No external program memory access is available. To begin executing code, tie the EA (external access) pin high.
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ADuC845/ADuC847/ADuC848 Data Sheet 5 V Part as op amps and voltage reference) can be powered from the AVDD supply line as well. For DVDD below 4.5 V, the internal POR holds the part in reset. As DVDD rises above 4.5 V, an internal timer times out for approximately 128 ms before the part is released from reset. The user must ensure that the power supply has reached a stable 4.75 V minimum level by this time.
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Data Sheet • • ADuC845/ADuC847/ADuC848 Cycling Power All registers are set to their default state and program execution starts at the reset vector approximately 128 ms later. Time Interval Counter (TIC) Interrupt If the OSC_PD bit in the PLLCON SFR is clear, the 32 kHz oscillator remains powered up even in power-down mode. If the time interval counter (wake-up/RTC timer) is enabled, a TIC interrupt wakes the part from power-down mode. The CPU services the TIC interrupt.
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ADuC845/ADuC847/ADuC848 Data Sheet Table 63. CHIPID Values for Σ-Δ MicroConverter Products a. PLACE ANALOG COMPONENTS HERE Part ADuC816 ADuC824 ADuC836 ADuC834 ADuC845/ADuC847/ADuC848 PLACE DIGITAL COMPONENTS HERE AGND DGND CHIPID 1xH 0xH 3xH 2xH AxH Clock Oscillator b. PLACE ANALOG COMPONENTS HERE As described earlier, the core clock frequency for the ADuC845/ ADuC847/ADuC848 is generated from an on-chip PLL that locks onto a multiple (384 times) of 32.768 kHz.
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Data Sheet ADuC845/ADuC847/ADuC848 DOΩNLOAD/DEBUG ENABLE JUMPER (NORMALLY OPEN) 1kΩ DVDD 1kΩ 11 P1.6/IEXC1/AIN7 4 AVDD 5 AGND 6 AGND XTAL2 35 7 REFIN– XTAL1 34 8 REFIN+ 56 P1.0/AIN1 1 P1.1/AIN2 AVDD ADuC845/ADuC847/ADuC848 RTD TxD DVDD 32.768kHz RxD RESET RREF 5.6kΩ LFCSP PACKAGE 17 18 19 DGND 0.1µF DVDD 200µA/400µA EXCITATION CURRENT 43 EA PSEN 44 2-PIN HEADER FOR EMULATION ACCESS (NORMALLY OPEN) 22 36 RESET ACTIVE HIGH.
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ADuC845/ADuC847/ADuC848 Data Sheet The serial port debugger is fully contained on the device, unlike ROM monitor type debuggers, and, therefore, no external memory is needed to enable in-system debug sessions. Single-Pin Emulation Mode Built into the ADuC845/ADuC847/ADuC848 is a dedicated controller for single-pin in-circuit emulation (ICE). In this mode, emulation access is gained by connection to a single pin, the EA pin.
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Data Sheet ADuC845/ADuC847/ADuC848 DOΩNLOAD/DEBUG ENABLE JUMPER (NORMALLY OPEN) 1kΩ DVDD 1kΩ 11 P1.6/IEXC1/AIN7 200µA/400µA EXCITATION CURRENT AVDD ADuC845/ADuC847/ADuC848 4 AVDD 0.1µF DGND LFCSP PACKAGE 5 AGND RTD DVDD 6 AGND XTAL2 35 7 REFIN– XTAL1 34 8 REFIN+ RREF 5.6kΩ 56 P1.0/AIN1 1 P1.1/AIN2 R 2 P1.2/AIN3/REFIN2+ 15 AIN9 R 16 AIN10 TxD 17 18 19 DVDD RxD DVDD DGND 3 P1.3/AIN4/REFIN2– RESET 22 36 RESET ACTIVE HIGH. (NORMALLY OPEN) DVDD 51 23 37 38 50 0.
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ADuC845/ADuC847/ADuC848 Data Sheet QuickStart DEVELOPMENT SYSTEM QuickStart-PLUS DEVELOPMENT SYSTEM The QuickStart Development System is an entry-level, low cost development tool suite supporting the ADuC8xx MicroConverter product family. The system consists of the following PC-based (Windows®-compatible) hardware and software development tools: The QuickStart-PLUS development system offers users enhanced nonintrusive debug and emulation tools.
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Data Sheet ADuC845/ADuC847/ADuC848 TIMING SPECIFICATIONS AC inputs during testing are driven at DVDD – 0.5 V for Logic 1 and 0.45 V for Logic 0. Timing measurements are made at VIH min for Logic 1 and VIL max for Logic 0 as shown in Figure 72. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded VOH/VOL level occurs as shown in Figure 72. CLOAD for all outputs = 80 pF, unless otherwise noted.
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ADuC845/ADuC847/ADuC848 Data Sheet Table 65. EXTERNAL DATA MEMORY READ CYCLE Parameter RD Pulse Width Address Valid After ALE Low Address Hold After ALE Low RD Low to Valid Data In Data and Address Hold After RD Data Float After RD ALE Low to Valid Data In Address to Valid Data In ALE Low to RD or WR Low Address Valid to RD or WR Low RD Low to Address Float RD or WR High to ALE High 12.58 MHz Core Clock Max Min 125 120 290 6.
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Data Sheet ADuC845/ADuC847/ADuC848 Table 66. EXTERNAL DATA MEMORY WRITE CYCLE Parameter tWLWH tAVLL tLLAX tLLWL tAVWL tQVWX tQVWH tWHQX tWHLH 12.58 MHz Core Clock Min Max 65 60 65 130 190 60 120 380 60 WR Pulse Width Address Valid After ALE Low Address Hold After ALE Low ALE Low to RD or WR Low Address Valid to RD or WR Low Data Valid to WR Transition Data Setup Before WR Data and Address Hold After WR RD or WR High to ALE High Min 130 120 135 6.
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ADuC845/ADuC847/ADuC848 Data Sheet tSUP SDATA (I/O) LSB MSB tDSU tPSU MSB tDSU 2-7 8 tL tF tDHD tR tRSU tH 1 PS ACK tDHD tSHD SCLK (I) tR 9 tSUP STOP START CONDITION CONDITION 1 S(R) REPEATED START Figure 75. I2C-Compatible Interface Timing Rev.
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Data Sheet ADuC845/ADuC847/ADuC848 Table 68.
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ADuC845/ADuC847/ADuC848 Data Sheet Table 69. SPI MASTER MODE TIMING (CPHA = 0) Parameter Min tSL tSH tDAV tDOSU tDSU tDHD tDF tDR tSR tSF Typ 635 635 Max 50 150 100 100 10 10 10 10 25 25 25 25 Characterized under the following conditions: a. Core clock divider bits CD2, CD1, and CD0 in PLLCON SFR set to 0, 1, and 1, respectively, that is, core clock frequency = 1.57 MHz. b. SPI bit-rate selection bits SPR1 and SPR0 in SPICON SFR set to 0 and 0, respectively.
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Data Sheet ADuC845/ADuC847/ADuC848 Table 70.
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ADuC845/ADuC847/ADuC848 Data Sheet Table 71.
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Data Sheet ADuC845/ADuC847/ADuC848 Table 72. UART TIMING (SHIFT REGISTER MODE) Parameter Min Serial Port Clock Cycle Time Output Data Setup to Clock Input Data Setup to Clock Input Data Hold After Clock Output Data Hold After Clock Min Variable Core_Clk Typ Max 12tcore 662 292 0 22 tXLXL TxD (OUTPUT CLOCK) SET RI OR SET TI tQVXH tXHQX RxD (OUTPUT DATA) BIT 1 LSB BIT 6 tDVXH RxD (INPUT DATA) LSB tXHDX BIT 1 Figure 80. UART Timing in Shift Register Mode Rev.
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ADuC845/ADuC847/ADuC848 Data Sheet OUTLINE DIMENSIONS 14.15 13.90 SQ 13.65 2.45 MAX 1.03 0.88 0.73 27 39 26 40 SEATING PLANE 7.80 REF TOP VIEW 2.10 2.00 1.95 0.23 0.11 VIEW A PIN 1 52 7° 0° 0.25 MIN 10.20 10.00 SQ 9.80 (PINS DOWN) 10° 6° 2° 14 13 1 0.10 COPLANARITY 0.38 0.22 LEAD WIDTH 0.65 BSC LEAD PITCH VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MO-112-AC-1 Figure 81. 52-Lead Metric Quad Flat Package [MQFP] (S-52-2) Dimensions shown in millimeters 0.30 0.23 0.18 0.
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Data Sheet ADuC845/ADuC847/ADuC848 ORDERING GUIDE Model 1, 2, 3 ADuC845BSZ62-5 ADuC845BSZ62-5-RL ADuC845BSZ62-3 ADuC845BSZ8-5 ADuC845BSZ8-5-RL ADuC845BSZ8-3 ADuC845BCPZ62-5 ADuC845BCPZ62-3 ADuC845BCPZ8-5 ADuC845BCPZ8-3 ADuC847BSZ62-5 ADuC847BSZ62-3 ADuC847BSZ32-5 ADuC847BSZ32-3 ADuC847BSZ8-5 ADuC847BSZ8-3 ADuC847BCPZ62-5 ADuC847BCPZ62-3 ADuC847BCPZ8-5 ADuC847BCPZ8-3 ADuC848BSZ62-5 ADuC848BSZ62-3 ADuC848BSZ32-5 ADuC848BSZ32-3 ADuC848BSZ8-5 ADuC848BSZ8-3 ADuC848BCPZ62-5 ADuC848BCPZ62-3 ADuC848BCPZ8-5 ADuC84
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ADuC845/ADuC847/ADuC848 Data Sheet NOTES Rev.
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Data Sheet ADuC845/ADuC847/ADuC848 NOTES Rev.
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ADuC845/ADuC847/ADuC848 Data Sheet NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04741-0-12/12(C) Rev.