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7 Caches and Tightly Coupled Memories

This chapter describes some aspects of initializing cached processors. It also describes processors with tightly

coupled memory, and ARMulator models of cached processors. It contains the following sections:

• About caches and tightly coupled memory

• System control coprocessor

• Memory protection units

• Configuring a PU

• Memory management units

• Configuring an MMU

• Tightly coupled memory.

See also ARM Architecture Reference Manual

and the Technical Reference Manual for your processor.

7.1 About caches and tightly coupled memory

Most modern processor cores can process instructions and data much faster than off-chip memory systems can

deliver them. Caches and Tightly Coupled Memories (TCMs) are different methods of improving system performance

when the external memory is narrow, slower than the core, or both.

Caches and TCMs are small, fast memories closely coupled with the processor. They can:

• enable good system performance even with slow or narrow off-chip memory

• reduce total system power consumption by reducing off-chip memory accesses.

Note

An uncached core is normally a better choice if off-chip memory is as fast as the core, and 32 bits wide.

7.1.1 About caches

Caches hold copies of the contents of memory locations. In general, these are memory locations that have been

loaded from recently. These copies are automatically used in preference to off-chip memory.

Caches only give an advantage if the cached memory locations are used again. In a real system this is very

common, for example:

• instruction loops

• frequently referenced data.

Cache operation is transparent to the programmer. However, you must initialize the core to specify what off-chip

memory locations are to be cached.

7.1.2 About tightly coupled memory

TCMs replace an area of off-chip memory when they are enabled.

TCM has the following advantages when compared with caches:

• it uses about half the die area

• it gives precisely predictable real-time performance.

To take advantage of a TCM, you must consider the TCM when writing your system software. For example, you are

likely to place the following in TCM:

• interrupt handling code

• data that changes frequently, such as the stack.

For further information see Tightly coupled memory.

7.1.3 Models of caches and tightly coupled memory

ARMulator models of processors that have caches or TCMs include models of the caches or TCMs.

To initialize the model caches or TCMs, you can program the PU or MMU models exactly as you program the real

hardware.

ARMulator Pagetable model

In addition, ARMulator includes a model, Pagetable, that can initialize the model caches or TCMs for you (see the

ARMulator Basics chapter in Debug Target Guide).

You can do any of the following:

Caches and Tightly Coupled Memories