User guide

7.3 Memory protection units

Protection Units (PUs) partition memory into regions. For each region you can specify:

Size

Typically this might range from 4KB to 4GB.

Base address

A region must start on a memory boundary that is a multiple of its size.

Access permissions

For example, you can mark a region for read access only from User mode.

When the PU is enabled, it aborts accesses to addresses outside any defined region.

7.3.1 Harvard architecture

ARM cached Harvard cores have separate instruction and data caches, but use the same bus to access external

memory. You can define the properties of memory regions for data and instructions separately.

Before you enable the PU, you must define:

• at least one memory region for instructions

• at least one memory region for data.

These can define the same region of memory.

7.3.2 Von Neumann architecture

Von Neumann cores access data and instructions over the same bus.

You must define at least one memory region before you enable the PU.

7.3.3 Overlapping regions

You can define overlapping memory protection regions. If several memory regions map the same memory, the PU

uses the highest numbered region to control access to the memory.

Figure 7-1 shows an example of memory regions. In this example, a background region covers the whole address

space. The foreground regions overlap the background region.

Figure 7-1 Example memory regions

Note

Instruction regions have corresponding data regions to allow for access to data contained in literal pools within code.

Caches and Tightly Coupled Memories