User guide

7.4.4 Configuring core operation

Coprocessor register c1 of CP15 is the core configuration register. You must use a read-modify-write cycle to alter

the contents of c1. Example 7-4 configures the core and enables the PU.

Example 7-4 Configuring core operation (ARM940T only)

MRC p15,0,r0,c1,c0,0 ; read core configuration register

ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode

ORR r0,r0,#0x1000 ; enable instruction cache

ORR r0,r0,#0x5 ; enable data cache and PU

MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration register

Table 7-3 shows the meanings of the core configuration bits for an ARM940T.

Table 7-3 Core configuration register (ARM940T)

[31] Asynchronous clocking select (iA)

[30] nFastBus select (nF)

[29:14] Reserved (must be zero, or use

read-modify-write)

[13] Alternate vectors select (V)

[12] Instruction cache enable flag (I)

[11:8] Reserved (must be zero, or use

read-modify-write)

[7] Big-end bit (E)

[6:3] Reserved (must be one, or use

read-modify-write)

[2] Data cache enable flag (D)

[1] Reserved (must be zero, or use

read-modify-write)

[0] PU enable (P)

Note

The details of the core configuration register vary from core to core. See the Technical Reference Manual for your

processor for details.

Caches and Tightly Coupled Memories