User guide

7.5.2 Memory access permissions and domains

Translation tables also hold access permission fields and a domain field.

There are 16 domains, Each region defined in the translation tables is controlled by the domain specified in the

corresponding domain field.

Each domain has two bits in the domain access control register in CP15. According to the value in these bits,

attempts to access regions belonging to the domain can:

• be allowed only if the permissions set in the translation table allow

• generate a domain fault

• be allowed regardless of the permissions set in the translation table.

When the processor generates a request for a memory access, the MMU checks the permissions as follows:

1. The MMU looks up the domain number in the translation table.

2. Using the domain number found in step 1, it checks the domain access permission for the domain in the domain

access control register.

3. According to the value found in the domain access control register, the MMU can either:

• allow the access unconditionally

• disallow the access unconditionally

• check the region access permissions in the translation table.

This system enables you to change context easily. For each application, an operating system can:

• allow free access, restricted access, or no access to different areas of memory

• change access permissions to large numbers of regions simultaneously by changing a single entry in the

domain access control register.

7.5.3 Cacheable and bufferable flags

Translation tables also hold cacheable and bufferable flags.

If you set a region to be cacheable:

• When you load from that region, the cache is searched. If the item is found, it is loaded from the cache. If the

item is not found, a complete cache line including the required address is loaded. Some other cache line is

evicted from the cache, unless there is an unused cache line available.

• When you save to that region, the cache is searched. If the item is found, the save is made to the cache. If the

item is not found, the save is made to memory.

The exact effect of the bufferable flag varies (see the Technical Reference Manual for your processor for details).

It is often desirable to prevent certain areas of memory being cached or buffered, for example:

• memory mapped I/O

• large arrays that you access randomly.

For full details, see ARM Architecture Reference Manual

and the Technical Reference Manual for your processor.

Caches and Tightly Coupled Memories