User guide

7.6 Configuring an MMU
To configure an MMU, you must do the following:
1. Build the translation table in memory. Translation tables include:
• virtual to physical translation
• cacheable and bufferable flags
• domain number
• access permissions.
See Building the translation table.
2. Store the location of the translation table in CP15 register c2 (see Setting the location of the translation table).
3. Enable the caches and enable the MMU by writing to CP15 register c1 (see Configuring core operation).
Note
The PageTable model can do this for you if you are using ARMulator (see Models of caches and tightly coupled
memory and the ARMulator Basics chapter in Debug Target Guide
).
You are recommended to:
• set permissions on the translation table for privileged mode access only
• map virtual addresses to identical physical addresses for the region containing the translation table.
7.6.1 Altering the translation table during program execution
You can alter the translation table without disabling the MMU. After doing this, you must flush the Translation
Lookaside Buffers (TLBs). For details, see ARM Architecture Reference Manual and the Technical Reference
Manual for your processor.
7.6.2 Building the translation table
Example 7-5 initializes a translation table that maps every virtual address to an identical physical address (this is
called flat mapping). It creates a table with 4096 entries for addresses 0x000xxxxx to 0xFFFxxxxx, with full access
for all regions.
Example 7-5 A flat translation table
LDR r0,=TTB ; Set start of translation table base (on 16KB boundary)
LDR r1, =0xFFF ; Set loop counter for 4096
MOV r2, #2_110000000000 ; Set access permissions for full access (bits 11:10)
ORR r2,r2,#2_000111100000 ; Set domain number to 15 (bits 8:5)
ORR r2,r2,#2_000000010000 ; Set bit 4 to 1
ORR r2,r2,#2_000000000010 ; Set as 1MB section (bits 1:0)
; All unused bits are 0
loop
ORR r3,r2,r1,LSL#20 ; Build pattern into empty register
STR r3,[r0,r1,LSL#2] ; Use loop counter to create individual table base addresse
s
SUBS r1,r1,#1 ; Decrement loop counter
BPL loop ; Loop until r1 goes negative
See Example 7-7 for an example of how to set up non-flat translations.
7.6.3 Setting the location of the translation table
Example 7-6 sets the translation table base register (c2) in CP15.
Example 7-6 Set translation table base
LDR r0,=TTB : Set start of translation table base (on 16KB boundary)
MCR p15,0,r0,c2,c2,0 ; Write value to CP15 c2
7.6.4 Aliasing a region
Example 7-7 shows how to alias a ROM region.
Example 7-7 Aliasing a ROM region at 0x0 to 0xFFF00000
LDR r0,=TTB : Set start of translation table base (on 16KB boundary)
Caches and Tightly Coupled Memories
Copyright ?1999 2001 ARM Limited 7-10