User guide

LDR r1,=0x0 ; Read first entry in translation table, which points to a 1MB sectio

n at 0x0

LDR r2,[r0,r1,LSL#2]

ORR r2,r2,#2_1000 ; Set cacheable flag

LDR r1,=0xFFF00000 ; Remap 0x0 to 0xFFF00000

STR r2,[r0,r1,LSL#2]

MOV r0,#0xC0000000 ; Set permissions for domain 15

MCR p15,0,r0,c3,c0,0 ; Write value to CP15 c3

7.6.5 Configuring core operation

Example 7-8 sets the bits in the core control register (c1) in CP15.

Example 7-8 Set core control parameters (ARM920T only)

MRC p15,0,r0,c1,c0,0 ; Read control register

ORR r0,r0,#0xC00000000 ; Set asynchronous clocking mode bits

ORR r0,r0,#0x1000 ; Set enable instruction cache bit

ORR r0,r0,#0x5 ; Set enable data cache and MMU bits

MCR p15,0,r0,c1,c0,0 ; Write to control register

Note

The details of the core configuration register vary from core to core. See the Technical Reference Manual for your

processor for details.

Caches and Tightly Coupled Memories