User guide

8.5 Polled debug communications
In addition to the comms data read and write registers, a comms data control register is provided by the debug
communications channel.
The following instruction returns the control register value in Rd:
MRC p14, 0, Rd, c0, c0
Two bits in this control register provide synchronized handshaking between the target and the host debugger:
Bit 1 (W bit)
Denotes whether the comms data write register is free (from the target point of view):
W = 0
New data can be written by the target application.
W = 1
The host debugger can scan new data out of the write register.
Bit 0 (R bit)
Denotes whether there is new data in the comms data read register (from the target point
of view):
R = 1
New data is available to be read by the target application.
R = 0
The host debugger can scan new data into the read register.
Note
The debugger cannot use coprocessor 14 to access the debug communications channel directly, because this has
no meaning to the debugger. Instead, the debugger can read from and write to the debug communications channel
registers using the scan chain. The debug communications channel data and control registers are mapped into
addresses in the EmbeddedICE logic, see Viewing EmbeddedICE logic registers.
The contents of the Embedded ICE logic registers can be viewed in armsd as coprocessor 0.
8.5.1 Viewing EmbeddedICE logic registers
You can view the EmbeddedICE logic registers in AXD:
• from the GUI: click on Processor Views, click on Registers, and select EICE, EICE Watch 0, or EICE Watch
1
• from the command line: type reg EICE.
Refer to MultiICE documentation for further information.
8.5.2 Target to debugger communication
This is the sequence of events for an application running on the ARM core to communicate with the debugger
running on the host:
1. The target application checks if the debug communications channel write register is free for use. It does this
using the MRC instruction to read the debug communications channel control register to check that the W bit is
clear.
2. If the W bit is clear, the debug communication write register is clear and the application writes a word to it using
the MCR instruction to coprocessor 14. The action of writing to the register automatically sets the W bit. If the W
bit is set, the debug communication write register has not been emptied by the debugger. If the application
needs to send another word, it must poll the W bit until it is clear.
3. The debugger polls the debug communication control register through scan chain 2. If the debugger sees that
the W bit is set, it can read the debug communications channel data register to read the message sent by the
application. The process of reading the data automatically clears the W bit in the debug communication control
register.
Example 8-1 shows how this works. The example code is available in
Install_directory\Examples\dcc\outchan.s.
Example 8-1
AREA OutChannel, CODE, READONLY
ENTRY
MOV r1,#3 ; Number of words to send
ADR r2, outdata ; Address of data to send
pollout
MRC p14,0,r0,c0,c0 ; Read control register
TST r0, #2
BNE pollout ; if W set, register still full
write
LDR r3,[r2],#4 ; Read word from outdata
Debug Communications Channel
Copyright ?1999 2001 ARM Limited 8-5