User guide

2.9 Floating-point options
The ATPCS supports two different floating-point hardware architectures and instruction sets:
The VFP architecture (see The VFP architecture).
The FPA architecture (see The FPA architecture). This is for backwards compatibility only.
Code for one architecture cannot be used on the other architecture.
The ADS compilers and assembler have six floating-point options:
-fpu VFP
-fpu FPA
-fpu softVFP
-fpu softVFP+VFP
-fpu softFPA
-fpu none.
If your target system has floating-point hardware, choose VFP, softVFP+VFP, or FPA.
Use softVFP+VFP if your system has floating-point hardware, and you want to use floating-point library routines
from Thumb code.
If your target system does not have floating-point hardware:
if you require compatibility with an FPA system, or objects produced under SDT, choose softFPA
if the module you are compiling or assembling does not use floating-point arithmetic, and you require
compatibility with both FPA and VFP systems, choose none
otherwise, choose softVFP. This is the default.
See also No floating-point hardware.
2.9.1 The VFP architecture
The VFP architecture has sixteen double-precision registers, d0-d15. Each double?precision register can be used as
two single-precision registers. As single-precision registers they are called s0-s31. d5 for example, is the same as
s10 and s11.
The VFP architecture does not support extended precision.
Vector and scalar modes
The VFP architecture has two modes of operation:
Scalar mode
Vector mode.
The ATPCS applies only to scalar mode operation. On entry to and exit from any publicly visible routine conforming
to the ATPCS the vector length and vector stride must both be set to 1.
Register usage with VFP
You can use the first eight double-precision registers, d0-d7:
to pass floating-point values into a routine
to pass floating-point values out of a routine
as scratch registers within a routine.
Each double-precision register can hold one double-precision value or two single-precision values. Floating-point
argument values are assigned to floating-point registers by assigning each value in turn to the next free register of
the appropriate type.
For example, in passing:
1.0 (double) 2.0 (double) 3.0 (single) 4.0 (double) 5.0 (single) 6.0 (single)
the assignment of parameter values to registers looks like:
To comply with ATPCS, if you use registers d8-d15 within a routine, you must save their values on entry and restore
them before exit. You can save them using a single FSTMX instruction and restore them using a single FLDMX
instruction. They are saved and restored as bit patterns, without interpretation as single or double-precision numbers.
N single-precision values saved occupy N+1 words.
Using the Procedure Call Standard
Copyright ?1999 2001 ARM Limited 2-12