User guide

• A BX instruction to branch to the Thumb code and change processor state.
The second section of the module, labelled ThumbProg, is prefixed by a CODE16 directive that instructs the
assembler to treat the following code as Thumb code. The Thumb code adds the contents of two registers together.
The processor is changed back to ARM state. The code again uses an ADR instruction to get the address of the
label, but this time the least significant bit is left clear. The BX instruction changes the state.
The third section of the code simply adds together the contents of two registers.
The final section labeled stop uses the semihosting SWI to report normal application exit. Refer to the Debug Target
Guide for more information on semihosting.
Note
The Thumb semihosting SWI is a different number from the ARM semihosting SWI (0xAB rather than 0x123456).
Example 3-2
AREA AddReg,CODE,READONLY ; Name this block of code.
ENTRY ; Mark first instruction to call.
main
ADR r0, ThumbProg + 1 ; Generate branch target address
; and set bit 0, hence arrive
; at target in Thumb state.
BX r0 ; Branch exchange to ThumbProg.
CODE16 ; Subsequent instructions are Thumb code.
ThumbProg
MOV r2, #2 ; Load r2 with value 2.
MOV r3, #3 ; Load r3 with value 3.
ADD r2, r2, r3 ; r2 = r2 + r3
ADR r0, ARMProg
BX r0
CODE32 ; Subsequent instructions are ARM code.
ARMProg
MOV r4, #4
MOV r5, #5
ADD r4, r4, r5
stop MOV r0, #0x18 ; angel_SWIreason_ReportException
LDR r1, =0x20026 ; ADP_Stopped_ApplicationExit
SWI 0x123456 ; ARM semihosting SWI
END ; Mark end of this file.
Building the example
To build and execute the example:
1. Enter the code using any text editor and save the file as addreg.s.
2. Type armasm -g addreg.s at the command prompt to assemble the source file.
3. Type armlink addreg.o -o addreg to link the file.
4. Type armsd addreg to load the module into the command-line debugger.
5. Type step to step through the rest of the program one instruction at a time. After each instruction, type reg to
display the registers. Watch the processor enter Thumb state. This is denoted by the T in the Current Program
Status Register (CPSR) changing from a lowercase t to an uppercase T.
3.2.4 ARM architecture v5T
In ARM architecture v5T and above:
• There are two additional interworking instructions available:
BLX address
The processor performs a pc-relative branch to address with link and changes
state. address must be within 32MB of the pc in ARM code, or within 4MB of the
pc in Thumb code.
BLX register
The processor performs a branch with link to an address contained in the specified
register. The value of bit[0] determines the new processor state.
In either case, bit[0] of lr is set to the current value of the Thumb bit in the CPSR. The means that the return
instruction can automatically return to the correct processor state.
Interworking ARM and Thumb
Copyright ?1999 2001 ARM Limited 3-4