User guide

ManualsBrandsARM ManualsComputer HardwareVERSION 1.2

5.1.1 The vector table

Processor exception handling is controlled by a vector table. The vector table is a reserved area of 32 bytes, usually

at the bottom of the memory map. It has one word of space allocated to each exception type, and one word that is

currently reserved.

This is not enough space to contain the full code for a handler, so the vector entry for each exception type typically

contains a branch instruction or load pc instruction to continue execution with the appropriate handler.

5.1.2 Use of modes and registers by exceptions

Typically, an application runs in User mode, but servicing exceptions requires privileged (that is, non-User mode)

operation. An exception changes the processor mode, and this in turn means that each exception handler has

access to a certain subset of the banked registers:

• its own r13 or Stack Pointer (sp_mode)

• its own r14 or Link Register (lr_mode)

• its own Saved Program Status Register (spsr_ mode).

In the case of a FIQ, each exception handler has access to five more general purpose registers (r8_FIQ to r12_FIQ).

Each exception handler must ensure that other registers are restored to their original contents upon exit. You can do

this by saving the contents of any registers the handler needs to use onto its stack and restoring them before

returning. If you are using Angel™ or ARMulator®, the required stacks are set up for you. Otherwise, you must set

them up yourself. See Chapter 6 Writing Code for ROM for more information.

Note

As supplied, the assembler does not predeclare symbolic register names of the form register_mode. To use this

form, you must declare the appropriate symbolic names with the RN assembler directive. For example, lr_FIQ RN

r14 declares the symbolic register name lr_FIQ for r14. See the directives chapter in Assembler Guide

for more

information on the RN directive.

5.1.3 Exception priorities

When several exceptions occur simultaneously, they are serviced in a fixed order of priority. Each exception is

handled in turn before execution of the user program continues. It is not possible for all exceptions to occur

concurrently. For example, the Undefined Instruction and SWI exceptions are mutually exclusive because they are

both triggered by executing an instruction.

Table 5-2 shows the exceptions, their corresponding processor modes and their handling priorities.

Because the Data Abort exception has a higher priority than the FIQ exception, the Data Abort is actually registered

before the FIQ is handled. The Data Abort handler is entered, but control is then passed immediately to the FIQ

handler. When the FIQ has been handled, control returns to the Data Abort handler. This means that the data

transfer error does not escape detection as it would if the FIQ were handled first.

Table 5-2 Exception priorities

Vector address Exception type Exception mode Priority (1=high, 6=low)

0x0

Reset Supervisor (SVC) 1

0x4

Undefined Instruction Undef 6

0x8

Software Interrupt (SWI) Supervisor (SVC) 6

0xC

Prefetch Abort Abort 5

0x10

Data Abort Abort 2

0x14

Reserved Not applicable Not applicable

0x18

Interrupt (IRQ) Interrupt (IRQ) 4

0x1C

Fast Interrupt (FIQ) Fast Interrupt (FIQ) 3

Handling Processor Exceptions