User guide

ManualsBrandsARM ManualsComputer HardwareVERSION 1.2

Returning from SWI and Undefined Instruction handlers

The SWI and Undefined Instruction exceptions are generated by the instruction itself, so the program counter is not

updated when the exception is taken. The processor stores (pc − 4) in lr_ mode. This makes lr_mode point to the

next instruction to be executed. Restoring the program counter from the lr with:

MOVS pc, lr

returns control from the handler.

The handler entry and exit code to stack the return address and pop it on return is:

STMFD sp!,{reglist,lr}

;...

LDMFD sp!,{reglist,pc}^

Returning from FIQ and IRQ handlers

After executing each instruction, the processor checks to see whether the interrupt pins are LOW and whether the

interrupt disable bits in the CPSR are clear. As a result, IRQ or FIQ exceptions are generated only after the program

counter has been updated. The processor stores (pc − 4) in lr_mode. This makes lr_mode point one instruction

beyond the end of the instruction in which the exception occurred. When the handler has finished, execution must

continue from the instruction prior to the one pointed to by lr_mode. The address to continue from is one word (four

bytes) less than that in lr_mode, so the return instruction is:

SUBS pc, lr, #4

The handler entry and exit code to stack the return address and pop it on return is:

SUB lr,lr,#4

STMFD sp!,{reglist,lr}

;...

LDMFD sp!,{reglist,pc}^

Returning from Prefetch Abort handlers

If the processor attempts to fetch an instruction from an illegal address, the instruction is flagged as invalid.

Instructions already in the pipeline continue to execute until the invalid instruction is reached, at which point a

Prefetch Abort is generated.

The exception handler loads the unmapped instruction into physical memory and uses the MMU, if there is one, to

map the virtual memory location into the physical one. The handler must then return to retry the instruction that

caused the exception. The instruction should now load and execute.

Because the program counter is not updated at the time the prefetch abort is issued, lr_ABT points to the instruction

following the one that caused the exception. The handler must return to lr_ABT − 4 with:

SUBS pc,lr, #4

The handler entry and exit code to stack the return address and pop it on return is:

SUB lr,lr,#4

STMFD sp!,{reglist,lr}

;...

LDMFD sp!,{reglist,pc}^

Returning from Data Abort handlers

When a load or store instruction tries to access memory, the program counter has been updated. The stored value of

(pc − 4) in lr_ABT points to the second instruction beyond the address where the exception occurred. When the

MMU, if present, has mapped the appropriate address into physical memory, the handler should return to the

original, aborted instruction so that a second attempt can be made to execute it. The return address is therefore two

words (eight bytes) less than that in lr_ABT, making the return instruction:

SUBS pc, lr, #8

The handler entry and exit code to stack the return address and pop it on return is:

SUB lr,lr,#8

STMFD sp!,{reglist,lr}

;...

LDMFD sp!,{reglist,pc}^

Handling Processor Exceptions