MSRNE SPSR_cxsf, r0 ; Restore the status.
LDMNEIA r13, {r0 - r14}^ ; Get the rest of the registers
NOP
SUBNES pc, lr, #4 ; and return and restore CPSR.
; Insert "no next process code" here.
Handling Processor Exceptions
Copyright ?1999 2001 ARM Limited 5-19
