User guide

5.11 Handling exceptions on Thumb-capable processors

This section describes the additional considerations you must take into account when writing exception handlers

suitable for use on Thumb-capable processors.

Thumb-capable processors use the same basic exception handling mechanism as processors that are not

Thumb-capable. An exception causes the next instruction to be fetched from the appropriate vector table entry.

Note

This section applies only to Thumb-capable ARM processors.

The same vector table is used for both Thumb-state and ARM-state exceptions. An initial step that switches to ARM

state is added to the exception handling procedure described in The processor response to an exception.

5.11.1 Thumb processor response to an exception

When an exception is generated, the processor takes the following actions:

1. Copies cpsr into spsr_mode.

2. Switches to ARM state.

3. Sets the CPSR mode bits.

4. Stores the return address in lr_mode. See The return address for further details.

5. Sets the program counter to the vector address for the exception. The switch from Thumb state to ARM state in

step 2 ensures that the ARM instruction installed at this vector address (either a branch or a pc-relative load) is

correctly fetched, decoded, and executed. This forces a branch to a top-level veneer that you must write in ARM

code.

Handling the exception

Your top-level veneer routine should save the processor status and any required registers on the stack. You then

have two options for writing the exception handler:

• Write the whole exception handler in ARM code.

• Perform a BX (Branch and eXchange) to a Thumb code routine that handles the exception. The routine must

return to an ARM code veneer in order to return from the exception, because the Thumb instruction set does

not have the instructions required to restore cpsr from spsr.

This second strategy is shown in Figure 5-4. See Chapter 3 Interworking ARM and Thumb for details of how to

combine ARM and Thumb code in this way.

Figure 5-4 Handling an exception in Thumb state

5.11.2 The return address

If an exception occurs in ARM state, the value stored in lr_mode is (pc − 4) as described in The return address and

return instruction. However, if the exception occurs in Thumb state, the processor automatically stores a different

value for each of the exception types. This adjustment is required because Thumb instructions take up only a

halfword, rather than the full word that ARM instructions occupy.

If this correction were not made by the processor, the handler would have to determine the original state of the

processor, and use a different instruction to return to Thumb code rather than ARM code. By making this adjustment,

however, the processor allows the handler to have a single return instruction that will return correctly, regardless of

the processor state (ARM or Thumb) at the time the exception occurred.

Handling Processor Exceptions