User guide

The following sections give a summary of the values to which the processor sets lr_mode if an exception occurs

when the processor is in Thumb state.

SWI and Undefined Instruction handlers

The handler's return instruction (MOVS pc,lr) changes the program counter to the address of the next instruction to

execute. This is at (pc − 2), so the value stored by the processor in lr_mode is (pc − 2).

FIQ and IRQ handlers

The handler's return instruction (SUBS pc,lr,#4) changes the program counter to the address of the next

instruction to execute. Because the program counter is updated before the exception is taken, the next instruction is

at (pc − 4). The value stored by the processor in lr_mode is therefore pc.

Prefetch Abort handlers

The handler's return instruction (SUBS pc,lr,#4) changes the program counter to the address of the aborted

instruction. Because the program counter is not updated before the exception is taken, the aborted instruction is at

(pc − 4). The value stored by the processor in lr_mode is therefore pc.

Data Abort handlers

The handler's return instruction (SUBS pc,lr,#8) changes the program counter to the address of the aborted

instruction. Because the program counter is updated before the exception is taken, the aborted instruction is at (pc −

6). The value stored by the processor in lr_mode is therefore (pc + 2).

5.11.3 Determining the processor state

An exception handler may need to determine whether the processor was in ARM or Thumb state when the exception

occurred. SWI handlers, especially, might need to read the processor state. This is done by examining the SPSR

T-bit. This bit is set for Thumb state and clear for ARM state.

Both ARM and Thumb instruction sets have the SWI instruction. When calling SWIs from Thumb state, you must

consider three things:

• the address of the instruction is at (lr − 2), rather than (lr − 4)

• the instruction itself is 16-bit, and so requires a halfword load (see Figure 5-5)

• the SWI number is held in 8 bits instead of the 24 bits in ARM state.

Figure 5-5 Thumb SWI instruction

Example 5-19 shows ARM code that handles a SWI from both sources. Consider the following points:

• Each of the do_swi_x routines could carry out a switch to Thumb state and back again to improve code density

if required.

• You can replace the jump table by a call to a C function containing a switch() statement to implement the

SWIs.

• It is possible for a SWI number to be handled differently depending upon the state it is called from.

• The range of SWI numbers accessible from Thumb state can be increased by calling SWIs dynamically (as

described in SWI handlers).

Example 5-19

T_bit EQU 0x20 ; Thumb bit of CPSR/SPSR, that is, bit 5.

SWIHandler

STMFD sp!, {r0-r3,r12,lr} ; Store registers.

MRS r0, spsr ; Move SPSR into general purpose register.

TST r0, #T_bit ; Occurred in Thumb state?

LDRNEH r0,[lr,#-2] ; Yes: load halfword and...

BICNE r0,r0,#0xFF00 ; ...extract comment field.

LDREQ r0,[lr,#-4] ; No: load word and...

BICEQ r0,r0,#0xFF000000 ; ...extract comment field.

Handling Processor Exceptions