User guide

6.2 Memory map considerations

A major consideration in the design of an embedded ARM application is the layout of the memory map, in particular

the memory that is situated at address 0x0. Following reset, the processor starts to fetch instructions from 0x0, so

there must be some executable code accessible from that address. In an embedded system, this requires ROM to be

present, at least initially, at address 0x0.

6.2.1 ROM at 0x0

The simplest layout is to locate the application in ROM at address 0 in the memory map (see Figure 6-1). The

application can then branch to the real entry point when it executes its first instruction (at the reset vector at address

0x0).

Figure 6-1 Example of a system with ROM at 0x0

However, there are disadvantages with this layout. ROM is typically narrow (8 or 16 bits) and slow (requires more

wait states to access it) compared to RAM. This slows down the handling of processor exceptions (especially

interrupts) through the vector table. Also, if the vector table is in ROM, it cannot be modified by the code.

For more information on exception handling, see Chapter 5 Handling Processor Exceptions.

6.2.2 RAM at 0x0

RAM is normally faster and wider than ROM. For this reason, it is better for the vector table and interrupt handlers if

the memory at 0x0 is RAM.

However, if RAM is located at address 0x0 on power-up, there is not a valid instruction in the reset vector entry.

Therefore, you must allow ROM to be located at 0x0 at power-up (so there is a valid reset vector), but to also allow

RAM to be located at 0x0 during normal execution. The changeover from the reset to the normal memory map is

normally caused by writing to a memory-mapped register (see Figure 6-2).

For example, on reset, an aliased copy of ROM is present at 0x0, but RAM is remapped to zero when code writes to

the RPS REMAP register. For more information, refer to the ARM Reference Peripheral Specification.

Figure 6-2 Example of a system with RAM at 0x0

Implementing RAM at 0x0

A sample sequence of events for implementing RAM at 0x0 is:

1. Power on to fetch the RESET vector at 0x0 (from the aliased copy of ROM).

Writing Code for ROM