Hardware manual

Common Features Description
2-20 Atmel 8051 Microcontrollers Hardware Manual
4316A–8051–01/04
Table 2-2. PSW: Program Status Word Register
2.2.4 Stack Pointer The Stack Pointer register is 8 bits wide. It is incremented before data is stored during
PUSH and CALL executions. While the stack may reside anywhere in on-chip RAM, the
Stack Pointer is initialized to 07H after a reset. This causes the stack to begin at location
08H.
2.2.5 Data Pointer The Data Pointer (DPTR) consists of a high byte (DPH) and a low byte (DPL). Its
intended function is to hold a 16-bit address. It may be manipulated as a 16-bit register
or as two independent 8-bit registers.
2.2.6 Ports 0 to 3 P0, P1, P2 and P3 are the SFR latches of Ports 0, 1, 2 and 3, respectively.
2.2.7 Serial Data Buffer The Serial Data Buffer is actually two separate registers, a transmit buffer and a receive
buffer register. When data is moved to SBUF, it goes to the transmit buffer where it is
held for serial transmission. (Moving a byte to SBUF is what initiates the transmission.)
When data is moved from SBUF, it comes from the receive buffer.
2.2.8 Timer Registers Register pairs (TH0, TL0), (TH1, TL1), and (TH2, TL2) are the 16-bit counting registers
for Timer/Counters 0, 1, and 2, respectively.
2.2.9 Capture Registers The register pair (RCAP2H, RCAP2L) are the capture register for the Timer 2 ‘capture
mode’. In this mode, in response to a transition at the 80C52’s T2EX pin, TH2 and TL2
are copied into RCAP2H and RCAP2L. Timer 2 also has a 16-bit auto-reload mode, and
RCAP2H and RCAP2L hold the reload value for this mode. More about Timer 2’s fea-
tures in Section 1.6.
(MSB) (LSB)
CY AC F0 RS1 RS0 OV - P
Symbol Position Name and Significance
CY PSW.7 Carry flag
AC PSW.6
Auxiliary Carry flag.
(For BCD operations.)
F0 PSW.5
Flag 0
(Available to the user for general purposes.)
RS1 PSW.4
Register bank Select control bits 1 & 0. Set/cleared
by software to determine working register bank (see
Note).
RS0 PSW.3
OV PSW.2 Overflow flag.
- PSW.1 (reserved)
PPSW.0
Parity flag.
Set/cleared by hardware each instruction cycle to
indicate and odd/even number of “one” bits in the
accumulator, i.e., even parity.
Note: The contents of (RS1, RS0) enable the working register banks as follows
(0.0)-Bank 0(00H-07H)
(0.1)-Bank 1(08H-0FH)
(1.0)-Bank 2(10H-17H)
(1.1)-Bank 3(18H-1FH)