Hardware manual

Common Features Description
2-22 Atmel 8051 Microcontrollers Hardware Manual
4316A–8051–01/04
2.4 CPU Timing
2.4.1 X1 Mode (Standard
Mode)
A machine cycle consists of 6 states (12 oscillator periods). Each state is divided into a
Phase 1 half, during which the Phase 1 clock is active, and a Phase 2 half, during which
the Phase 2 clock is active. Thus, a machine cycle consists of 12 oscillator periods,
numbered S1P1 (State 1, Phase 1), through S6P2 (State 6, Phase 2). Each phase lasts
for one oscillator period. Each state lasts for two oscillator periods. Typically, arithmetic
and logical operations take place during Phase 1 and internal register-to-register trans-
fers take place during Phase 2.
The diagrams in Figure 2-3 show the fetch/execute timing referenced to the internal
states and phases. Since these internal clock signals are not user accessible, the
XTAL2 oscillator signal and the ALE (Address Latch Enable) signal are shown for exter-
nal reference. ALE is normally activated twice during each machine cycle: once during
S1P2 and S2P1, and again during S4P2 and S5P1.
Execution of one-cycle instruction begins at S1P2, when the opcode is latched into the
Instruction Register. If it is a two-byte instruction, the second byte is read during S4 of
the same machine cycle. If it is one-byte instruction, there is still a fetch at S4, but the
byte read (which would be the next opcode), is ignored, and the Program Counter is not
incremented. In any case, execution is complete at the end of S6P2. Figure 2-3A and
Figure 2-3B show the timing for a 1-byte, 1-cycle instruction and for a 2-byte, 1-cycle
instruction.
Most 80C51 instructions execute in one cycle. MUL (multiply) and DIV (divide) are the
only instructions that take more than two cycles to complete. They take four cycles.
Separately, two codes bytes are fetched from Program Memory during every machine
cycle. The only exception to this is when a MOVX instruction is executed. MOVX is a 1-
byte 2-cycle instruction that accesses external Data Memory. During a MOVX, two
fetches are skipped while the external Data Memory is being addressed and strobed.
Figure 2-3C and Figure 2-3D show the timing for a normal 1-byte, 2-cycle instruction
and for a MOVX instruction.