Hardware manual

Common Features Description
2-26 Atmel 8051 Microcontrollers Hardware Manual
4316A–8051–01/04
in the data sheets) when externally pulled low. Port 0, on the other hand, is considered
“true” bidirectional, because when configured as an input it floats.
All the port latches in the 80C51 have 1’s written to them by the reset function. If a 0 is
subsequently written to a port latch, it can be re configured as an input by writing a 1 to
it.
2.5.2 Writing to a Port In the execution of an instruction that changes the value in a port latch, the new value
arrives at the latch during S6P2 of the final cycle of the instruction. However, port
latches are in fact sampled by their output buffers only during Phase 1 of any clock
period. (During Phase 2 the output buffer holds the value it saw during the previous
Phase 1). Consequently, the new value in the port latch won’t actually appear at the out-
put pin until the next Phase 1, which be at S1P1 of the next machine cycle.
If the change requires a 0-to-1 transition in Port 1, 2, or 3, an additional pull-up is turned
on during S1P1 and S1P2 of the cycle in which the transition occurs. This is done to
increase the transition speed. The extra pull-up can source about 100 times the current
that the normal pull-up can. It should be noted that the internal pull-ups are field-effect
transistors, not linear resistors. The pull-up arrangements are shown in Figure 2-5.
In the CMOS versions, the pull-up consists of three pFETs. It should be noted that an n-
channel FET (nFET) is turned on when a logical 1 is applied to its gate, and is turned off
when a logical 0 is applied to its gate. A p-channel FET (pFET) is the opposite: it is on
when its gate sees a 0, and off when its gate sees a 1.
pFET 1 in Figure 2-5 is the transistor that is turned on 2 oscillator periods after a 0-to-1
transition in the port latch. While it’s on, it turns on pFET 3 (a weak pull-up), through the
inverter. This inverter and pFET form a latch which hold the 1.
Note that if the pin is emitting a 1, a negative glitch on the pin from some external source
can turn off pFET 3, causing the pin to go into a float state, pFET 2 is a very weak pull-
up which is on whenever the nFET is off, in traditional CMOS style. It’s only about 1/10
the strength of pFET3. Its function is to restore a 1 to the pin in the event the pin had a 1
and lost it to a glitch.
Figure 2-5. Ports 1 and 3 CMOS Internal Pull-up Configurations.
Port 2 is similar except that it holds the strong pull-up on while emitting 1s that are address bits.
(See “Accessing External Memory”.)
2.5.3 Port Loading and
Interfacing
The output buffer of Ports 1, 2 and 3 can each drive 3LS TTL inputs. The pins can be
driven by open-collector and open-drain outputs, but note that 0-to-1 transition will not
be fast. In the CMOS device, an input 0 turns off pull-up P3, leaving only the weak pull-
CMOS Configuration. pFET 1 is turned on f
or
2 osc. periods after Q makes a 1-to-0 tran
si-
tion. During this time, pFET 1 also turns o
n
pFET 3 through the inverter to form a latc
h
which holds the 1. pFET 2 is also on.