Hardware manual

Common Features Description
2-28 Atmel 8051 Microcontrollers Hardware Manual
4316A–8051–01/04
CLR PX.Y(clear bit Y of Port X)
SETB PX.Y(set bit Y of Port X)
It is not obvious that the last three instructions in this list are read-modify-write instruc-
tions, but they are. They read the port byte, all 8 bits, modify the addressed bit, then
write the new byte back to the latch.
The reason that read-modify-write instructions are directed to the latch rather than the
pin is to avoid a possible misinterpretation of the voltage level at the pin. For example, a
port bit might be used to drive the base of a transistor. When a 1 is written to the bit, the
transistor is turned on. If the CPU then reads the same port bit at the pin rather than the
latch, it will read the base voltage of the transistor and interpret it as a 0. Reading the
latch rather than the pin will return the correct value of 1.
2.6 Accessing
External Memory
Accesses to external memory are of two types: accesses to external Program Memory
and accesses to external Data Memory. Accesses to external Program Memory use sig-
nal PSEN
(program store enable) as the read strobe. Accesses to external Data Memory use
RD
or WR (alternate function of P3.7 and P3.6) to strobe the memory.
Fetches from external Program memory always use a 16-bit address. Accesses to
external Data Memory can use either a 16-bit address (MOVX @DPTR) or an 8-bit
address (MOVX @Ri).
Whenever a 16-bit address is used, the high byte of the address comes out on Port 2,
where it is held for the duration of the read or write cycle. Note that the Port 2 drivers use
the strong pull-ups during the entire time that they are emitting address bits that are 1’s.
This is during the execution of a MOVX @DPTR instruction. During this time the Port 2
latch (the Special Function register) does not have to contain 1’s, and the contents of
the Port 2 SFR are not modified. If the external memory cycle is not immediately fol-
lowed by another external memory cycle, the undisturbed contents of the Port 2 SFR will
reappear in the next cycle.
If an 8-bit address is being used (MOVX @Ri), the contents of the Port 2 SFR remain at
the Port 2 pins throughout the external memory cycle. This will facilitate paging.
In any case, the low byte of the address is time-multiplexed with the data byte on Port 0.
The ADDR/DATA signal drives both FETs in the Port 0 output buffers. Thus, in this
application the Port 0 pins are not open-drain outputs, and do not require external pull-
ups. Signal ALE (address latch enable) should be used to capture the address byte into
an external latch. The address byte is valid at the negative transitions of ALE. Then, in a
write cycle, the data byte to be written appears on Port 0 just before WR
is activated, and
remains there until after WR
is deactivated. In a read cycle, the incoming byte is accepted at
Port 0 just before the read strobe is deactivated.
During any access to external memory, the CPU writes 0FFH to the Port 0 latch (the
Special Function Register), thus obliterating whatever information the Port 0 SFR may
have been holding.
External program Memory is accessed under two conditions:
1. Whenever signal EA
is active or
2. Whenever the program counter (PC) contains a number that is larger than the
memory size.
This requires that the ROMless versions have EA
wired low to enable the lower program
bytes to be fetched from external memory.