Hardware manual

Common Features Description
Atmel 8051 Microcontrollers Hardware Manual 2-31
4316A–8051–01/04
2.9 Timer/Counters The Atmel 80C51 Microcontrollers implement two general purpose, 16-bit tim-
ers/counters. They are identified as Timer 0 and Timer 1, and can be independently
configured to operate in a variety of modes as a timer or as an event counter. When
operating as a timer, the timer/counter runs for a programmed length of time, then
issues an interrupt request. When operating as a counter, the timer/counter counts neg-
ative transitions on an external pin. After a preset number of counts, the counter issues
an interrupt request.
The various operating modes of each timer/counter are described in the following
sections.
2.9.1 Timer/Counter
Operations
A basic operation consists of timer registers THx and TLx (x= 0, 1) connected in cas-
cade to form a 16-bit timer. Setting the run control bit (TRx) in TCON register (see
Figure 2-4) turns the timer on by allowing the selected input to increment TLx. When
TLx overflows it increments THx; when THx overflows it sets the timer overflow flag
(TFx) in TCON register. Setting the TRx does not clear the THx and TLx timer registers.
Timer registers can be accessed to obtain the current count or to enter preset values.
They can be read at any time but TRx bit must be cleared to preset their values, other-
wise the behavior of the timer/counter is unpredictable.
The C/Tx# control bit (in TCON register) selects timer operation, or counter operation,
by selecting the divided-down peripheral clock or external pin Tx as the source for the
counted signal. TRx bit must be cleared when changing the mode of operation, other-
wise the behavior of the timer/counter is unpredictable.
For timer operation (C/Tx# = 0), the timer register counts the divided-down peripheral
clock. The timer register is incremented once every peripheral cycle (6 peripheral clock
periods). The timer clock rate is F
PER
/ 6, i.e. F
OSC
/ 12 in standard mode or F
OSC
/ 6 in
X2 mode.
For counter operation (C/Tx# = 1), the timer register counts the negative transitions on
the Tx external input pin. The external input is sampled every peripheral cycle. When
the sample is high in one cycle and low in the next one, the counter is incremented.
Since it takes 2 cycles (12 peripheral clock periods) to recognize a negative transition,
the maximum count rate is F
PER
/ 12, i.e. F
OSC
/ 24 in standard mode or F
OSC
/ 12 in X2
mode. There are no restrictions on the duty cycle of the external input signal, but to
ensure that a given level is sampled at least once before it changes, it should be held for
at least one full peripheral cycle.
In addition to the “timer” or “counter” selection, Timer 0 and Timer 1 have four operating
modes from which to select which are selected by bit-pairs (M1, M0) in TMOD. Modes 0, 1,
and 2 are the same for both timer/counters. Mode 3 is different. The four operating modes are
described below.
Timer 2, has three modes of operation: ‘capture’, ‘auto-reload’ and ‘baud rate
generator’.
2.10 Timer 0 Timer 0 functions as either a timer or event counter in four modes of operation. Figure 2-
9 to Figure 2-12 show the logical configuration of each mode.
Timer 0 is controlled by the four lower bits of the TMOD register (see Table 2-5) and bits
0, 1, 4 and 5 of the TCON register (see Table 2-4). TMOD register selects the method of
timer gating (GATE0), timer or counter operation (T/C0#) and mode of operation (M10
and M00). The TCON register provides timer 0 control functions: overflow flag (TF0), run
control bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0).