Hardware manual

Common Features Description
2-32 Atmel 8051 Microcontrollers Hardware Manual
4316A–8051–01/04
For normal timer operation (GATE0= 0), setting TR0 allows TL0 to be incremented by
the selected input. Setting GATE0 and TR0 allows external pin INT0# to control timer
operation.
Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag, generating an inter-
rupt request.
It is important to stop timer/counter before changing mode.
2.10.1 Mode 0 (13-bit
Timer)
Mode 0 configures timer 0 as a 13-bit timer which is set up as an 8-bit timer (TH0 regis-
ter) with a modulo 32 prescaler implemented with the lower five bits of the TL0 register
(see Figure 2-9). The upper three bits of TL0 register are indeterminate and should be
ignored. Prescaler overflow increments the TH0 register.
As the count rolls over from all 1’s to all 0’s, it sets the timer interrupt flag TF0. The
counted input is enabled to the Timer when TR0 = 1 and either GATE = 0 or INT0
= 1.
(Setting GATE = 1 allows the Timer to be controlled by external input INT0
, to facilitate pulse
width measurements). TR0 is a control bit in the Special Function register TCON (Table 2-4).
GATE is in TMOD.
The 13-bit register consists of all 8 bits of TH0 and the lower 5 bits of TL0. The upper 3
bits of TL0 are indeterminate and should be ignored. Setting the run flag (TR0) does not
clear the registers.
Mode 0 operation is the same for Timer 0 as for Timer 1. Substitute TR0, TF0 and INT0
for the corresponding Timer 1 signals in Table 2-10. There are two different GATE bits, one for
Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).
Figure 2-9. Timer/Counter x (x = 0 or 1) in Mode 0
2.10.2 Mode 1 (16-bit
Timer)
Mode 1 is the same as Mode 0, except that the Timer register is being run with all 16
bits.
Mode 1 configures timer 0 as a 16-bit timer with the TH0 and TL0 registers connected in
cascade (see Figure 2-10). The selected input increments the TL0 register.
PERIPH
CLOCK
TRx
TCON reg
TFx
TCON reg
0
1
GATE
÷ 6
Overflow
Timer x
Interrupt
Request
C/Tx#
TMOD reg
TLx
(5 bits)
THx
(8 bits)
INTx#
Tx
TMOD reg