Hardware manual

Common Features Description
2-36 Atmel 8051 Microcontrollers Hardware Manual
4316A–8051–01/04
Figure 2-15. Timer Interrupt System
2.11.6 Timer Registers Table 2-4. TCON Register - TCON (S:88h)
Timer/Counter Control Register.
Reset Value = 0000 0000b
TF0
TCON.5
ET0
IE0.1
Timer 0
Interrupt Request
TF1
TCON.7
ET1
IE0.3
Timer 1
Interrupt Request
76543210
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Bit
Number
Bit
Mnemonic Description
7TF1
Timer 1 Overflow Flag
Cleared by hardware when processor vectors to interrupt routine.
Set by hardware on timer/counter overflow, when the timer 1 register overflows.
6TR1
Timer 1 Run Control Bit
Clear to turn off timer/counter 1.
Set to turn on timer/counter 1.
5TF0
Timer 0 Overflow Flag
Cleared by hardware when processor vectors to interrupt routine.
Set by hardware on timer/counter overflow, when the timer 0 register overflows.
4TR0
Timer 0 Run Control Bit
Clear to turn off timer/counter 0.
Set to turn on timer/counter 0.
3IE1
Interrupt 1 Edge Flag
Cleared by hardware when interrupt is processed if edge-triggered (see IT1).
Set by hardware when external interrupt is detected on INT1# pin.
2IT1
Interrupt 1 Type Control Bit
Clear to select low level active (level triggered) for external interrupt 1 (INT1#).
Set to select falling edge active (edge triggered) for external interrupt 1.
1IE0
Interrupt 0 Edge Flag
Cleared by hardware when interrupt is processed if edge-triggered (see IT0).
Set by hardware when external interrupt is detected on INT0# pin.
0IT0
Interrupt 0 Type Control Bit
Clear to select low level active (level triggered) for external interrupt 0 (INT0#).
Set to select falling edge active (edge triggered) for external interrupt 0.