Hardware manual

Atmel 8051 Microcontrollers Hardware Manual 1-1
Rev. 4316A–8051–01/04
Section 1
The 8051 Instruction Set
The 8051 instruction set is optimized for 8-bit control applications. It provides a variety of
fast addressing modes for accessing the internal RAM to facilitate byte operations on
small data structures. The instruction set provides extensive support for one-bit vari-
ables as a separate data type, allowing direct bit manipulation in control and logic
systems that require Boolean processing.
An overview of the 8051 instruction set is presented below, with a brief description of
how certain instructions might be used.
1.1 Program Status
Word
The Program Status Word (PSW) contains several status bits that reflect the current
state of the CPU. The PSW, shown in Table 1-1 on page 2, resides in SFR space. It
contains the Carry bit, the Auxiliary Carry (for BCD operations), the two register bank
select bits, the Overflow flag, a parity bit, and two user-definable status flags.
The Carry bit, other than serving the functions of a Carry bit in arithmetic operations,
also serves as the “Accumulator” for a number of Boolean operations.
The bits RS0 and RS1 are used to select one of the four register banks shown below.
A number of instructions refer to these RAM locations as R0 through R7. The selection
of which of the four banks is being referred to is made on the basis of the bits RS0 and
RS1 at execution time.
The parity bit reflects the number of 1’s in the Accumulator: P = 1 if the Accumulator
contains an odd number of 1’s, and P = 0 if the Accumulator contains an even number of
1’s. Thus the number of 1’s in the Accumulator plus P is always even.
Two bits in the PSW are uncommitted and may be used as general purpose status flags.
The PSW register contains program status information as detailed in Table 1-1.