Hardware manual

Common Features Description
Atmel 8051 Microcontrollers Hardware Manual 2-51
4316A–8051–01/04
Figure 2-23. Timer 2 Generated Commonly Used Baud Rates
XX-XX are values of RCAP2H-RCAP2L
2.13.6 More About Mode 0 Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are trans-
mitted/received: 8 data bits (LSB first). The baud rate is fixed at 1/12 the oscillator
frequency.
Figure 2-24 shows a simplified functional diagram of the serial port in mode 0, and asso-
ciated timing.
Transmission is initiated by any instruction that uses SBUF as a destination register.
The “write to SBUF” signal at S6P2 also loads a 1 into the 9th bit position of the transmit
shift register and tells the TX Control block to commence a transmission. The internal
timing is such that one full machine cycle will elapse between “write to SBUF”, and acti-
vation of SEND.
SEND enables the output of the shift register to the alternate output function line of P3.0,
and also enables SHIFT CLOCK to the alternate output function line of P3.1. SHIFT
CLOCK is low during S3, S4, and S5 of every machine cycle, and high during S6, S1
and S2. At S6P2 of every machine cycle in which SEND is active, the contents of the
transmit shift register are shifted to the right one position.
As data bits shift out to the right, zeros come in from the left. When the MSB of the data
byte is at the output position of the shift register, then the 1 that was initially loaded into
the 9th position, is just to the left of the MSB, and all positions to the left of that contain
zeros. This condition flags the TX Control block to do one last shift and then deactivate
SEND and set T1. Both of these actions occur at S1P1 of the 10th machine cycle after
“write to SBUF.”
Reception is initiated by the condition REN = 1 and RI = 0. At S6P2 of the next machine
cycle, the RX Control unit writes the bits 11111110 to the receive shift register, and in
the next clock phase activates RECEIVE.
RECEIVE enables SHIFT CLOCK to the alternate output function line of P3.1. Shift
CLOCK makes transitions at S3P1 and S6P1 of every machine cycle. At S6P2 of every
cycle in which RECEIVE is active, the contents of the receive shift register are shifted to
the left one position. The value that comes in from the right is the value that was sam-
pled at the P3.0 pin at S5P2 of the same machine cycle.
Fosc (MHz) 6 11.0592 12 16
Baudrate (RCAP2H -
RACP2L)
110 F9-57 EE-3F
300 FD-8F FB-80 FB-1E F9-7D
600 FE-C8 FD-C0 FD-8F FC-BF
1200 FF-64 FE-E0 FE-C8 FE-5F
2400 FF-B2 FF-70 FF-64 FF-30
4800 FF-D9 FF-B8 FF-B2 FF-98
9600 FF-DC FF-D9 FF-CC
19200 FF-EE FF-E6
38400 FF-F7 FF-F3
56800 FF-FA