Hardware manual

Common Features Description

2-52 Atmel 8051 Microcontrollers Hardware Manual

4316A–8051–01/04

As data bits come in from the right, 1’s shift out to the left. When the 0 that was initially

loaded into the rightmost position arrives at the leftmost position in the shift and load

SBUF. At S1P1 of the 10th machine cycle after the write to SCON that cleared RI,

RECEIVE is cleared and RI is set.

2.13.7 More About Mode 1 Ten bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data

bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. In the

80C51 the baud rate is determined by the Timer 1 overflow rate. In the microcontroller

having Timer 2 feature, it is determined either by the Timer 1 overflow rate, or the Timer

2 overflow rate, or both (one for transmit and the other for receive).

Figure 2-25 shows a simplified functional diagram of the serial port in Mode 1, and asso-

ciated timings for transmit and receive.

Transmission is initiated by any instruction that uses SBUF as a destination register.

The “write to SBUF” signal also loads a 1 into the 9th bit position of the transmit shift

actually commences at S1P1 of the machine cycle following the next rollover in the

divide-by-16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter,

not to the “write to SBUF” signal).

The transmission begins with activation of SEND

, which puts the start bit at TXD. One bit

time later, DATA is activated, which enables the output bit of the transmit shift register to TXD.

The first shift pulse occurs one bit time after that.

As data bits shift out to the right, zeros are clocked in from the left. When the MSB of the

data byte is at the output position of the shift register, then the 1 that was initially loaded

into the 9th position is just to the left of the MSB, and all positions to the left of that con-

tain zeroes. This condition flags the TX Control unit to do one last shift and then

deactivate SEND

and set TI. This occurs at the 10th divide-by-16 rollover after “write to SBUF”.

Reception is initiated by a detected 1-to-0 transition at RXD. For this purpose RXD is

sampled at a rate of 16 times whatever baud rate has been established. When a transi-

tion is detected, the divide-by-16 counter is immediately reset, and 1FFH is written into

the input shift register. Resetting the divide-by-16 counter aligns its rollovers with the

boundaries of the incoming bit times.