Hardware manual

Common Features Description
2-62 Atmel 8051 Microcontrollers Hardware Manual
4316A–8051–01/04
Reset Value = XXX0 0000b
Not bit addressable
2.16 Interrupts If two requests of different priority Ievels are received simultaneously, the request of
higher priority level is serviced. If requests of the same priority level are received
simultaneously, an internal polling sequence determine which request is serviced, Thus
within each priority level is a second priority structure determined by the polling
sequence, as follows:
Note that the "priority within level" structure is only used to resolve simultaneous
requests of the same priority level.
Table 2-29. BDRCON Register
BDRCON - Baud Rate Control Register (9Bh)
76543210
- - - BRR TBCK RBCK SPD SRC
Bit
Number
Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4BRR
Baud Rate Run Control bit
Cleared to stop the internal Baud Rate Generator.
Set to start the internal Baud Rate Generator.
3TBCK
Transmission Baud rate Generator Selection bit for UART
Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
2RBCK
Reception Baud Rate Generator Selection bit for UART
Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
1SPD
Baud Rate Speed Control bit for UART
Cleared to select the SLOW Baud Rate Generator.
Set to select the FAST Baud Rate Generator.
0SRC
Baud Rate Source select bit in Mode 0 for UART
Cleared to select F
OSC
/12 as the Baud Rate Generator (F
CLK PERIPH
/6 in X2 mode).
Set to select the internal Baud Rate Generator for UARTs in mode 0.
Table 2-30. Interrupt Priority Level
Source Priority Within Level
1 IE0 (highest)
2TF0
3IE1
4TF1
5RI + TI
6 TF2 + EXF2 (lowest)