Hardware manual

Common Features Description
2-64 Atmel 8051 Microcontrollers Hardware Manual
4316A–8051–01/04
The hardware-generated LCALL pushes the contents of the Program Counter onto the
stack (but it does not save the PSW) and reloads the PC with an address that depends
on the source of the interrupt being vectored to, as shown below.
Execution proceeds from that location until the RETI instruction is encountered. The
RETI instruction informs the processor that this interrupt routine is no longer in
progress, then pops the top two bytes from the stack and reloads the Program Counter.
Execution of the interrupted program continues from where it left off.
Note that a simple RET instruction would also have returned execution to the
interrupted program, but it would have left the interrupt control system thinking an
interrupt was still in progress.
2.16.2 External Interrupts The external sources can be programmed to be level-activated or transition-activated
by setting or clearing bit IT1 or ITO in Register TCON.
If ITx = O, external interrupt x is triggered by a detected low at the INTx
pin. If ITx = 1,
external interrupt x is edge-triggered. In this mode if successive samples of the INTx
pin show a high in one cycle and a low in the next cycle, interrupt request flag IEx in
TCON is set. Flag bit IEx then requests the interrupt.
Since the external interrupt pins are sampled once each machine cycle, an input high
or low should hold for at least 12 oscillator periods to ensure sampling. If the external
interrupt is transition-activated, the external source has to hold the request pin high for
at least one cycle, and then hold it low for at least one cycle to ensure that the
transition is seen so that interrupt request flag IEx will be set. IEx will be automatically
cleared by the CPU when the service routine is called.
If the external interrupt is level-activated, the external source has to hold the request
active until the requested interrupt is actually generated. Then it has to deactivate the
request before the interrupt service routine is completed, or el se another interrupt will
be generated.
2.16.3 Response Time The INTO
and INT1 levels are inverted and latched into IEO and IE1 and S5P2 of
every machine cycle. The values are not actualIy polIed by the circuitry until the next
machine cycle. If a request is active and conditions are right for it to be acknowledged,
a hardware subroutine calI to the requested service routine will be the next instruction
to be executed. The calI itself takes two cycles. Thus, a minimum of three complete
machine cycles elapse between activation of an external interrupt request and the
beginning of execution of the service routine. Figure 29. shows interrupt response
timings.
A longer response time would result if the request is blocked by one of the 3 previously
listed conditions. If an interrupt of equal or higher priority level is already in progress,
the additional wait time obviously depends on the nature of the other interrupt’s service
routine. If the instruction in progress is not in its final cycle, the additional wait time
cannot be more than 3 cycles, since the longest instructions (MUL and DIV) are only 4
cycles long, and if the instruction in progress is RETI or an access to IE or IP, the
additional wait time cannot be more than 5 cycles (a maximum of one more cycle to
Source Vector Address
IE0 0003H
TF0 000BH
IE1 0013H
TF1 001BH
RI + TI 0023H
TF2 + EXF2 002BH