Datasheet

ManualsBrandsBROADCOM ManualsOptoelectronics & DisplaysLogicGate Optocoupler SO 8 Type (misc.) 10 MBd, 45 ns, 2-channel

Features

• HCMOS/LSTTL/TTL performance compatible

• 1000 V/µs minimum Common Mode Rejection (CMR)

at V

= 50 V (HCPL-261A family) and 15 kV/µs

minimum CMR at V

= 1000 V (HCPL-261N family)

• High speed: 10 MBd typical

• AC and DC performance specied over industrial

temperature range -40°C to +85°C

• Available in 8 pin DIP, SOIC-8 packages

• Safety approval:

– UL recognized per UL1577 3750 V rms for 1 minute

and 5000 V

rms for 1 minute (Option 020)

– CSA Approved

– IEC/EN/DIN EN 60747-5-2 approved

Applications

• Low input current (3.0 mA) HCMOS compatible

version of 6N137 optocoupler

• Isolated line receiver

• Simplex/multiplex data transmission

• Computer-peripheral interface

• Digital isolation for A/D, D/A conversion

• Switching power supplies

• Instrumentation input/output isolation

• Ground loop elimination

• Pulse transformer replacement

HCPL-261A, HCPL-061A, HCPL-263A, HCPL-063A

HCPL-261N, HCPL-061N, HCPL-263N, HCPL-063N

HCMOS Compatible, High CMR, 10 MBd Optocouplers

Data Sheet

The connection of a 0.1 µF bypass capacitor between pins 5 and 8 is

required.

CATHODE

ANODE

GND

HCPL-261A Functional Diagram

ANODE

CATHODE

ANODE

GND

HCPL-261A/261N

HCPL-061A/061N

HCPL-263A/263N

HCPL-063A/063N

SHIELD SHIELD

LED

OFF

ENABLE

OUTPUT

TRUTH TABLE

(POSITIVE LOGIC)

LED

OFF

OUTPUT

TRUTH TABLE

(POSITIVE LOGIC)

Description

The HCPL-261A family of optically coupled gates shown

on this data sheet provide all the benets of the in-

dustry standard 6N137 family with the added benet

of HCMOS compatible input current. This allows direct

interface to all common circuit topologies without ad-

ditional LED buer or drive components. The AlGaAs

LED used allows lower drive currents and reduces

degradation by using the latest LED technology. On

the single channel parts, an enable output allows the de-

tector to be strobed. The output of the detector IC is an

open collector schottky-clamped transistor. The internal

shield provides a minimum common mode transient im-

munity of 1000 V/µs for the HCPL-261A family and 15000

V/µs for the HCPL-261N family.

Functional Diagram

CAUTION: It is advised that normal static precautions be taken in handling and assembly

of this component to prevent damage and/or degradation which may be induced by ESD.

Lead (Pb) Free

RoHS 6 fully

compliant

RoHS 6 fully compliant options available;

-xxxE denotes a lead-free product

Summary of content (17 pages)

PAGE 1
HCPL-261A, HCPL-061A, HCPL-263A, HCPL-063A HCPL-261N, HCPL-061N, HCPL-263N, HCPL-063N HCMOS Compatible, High CMR, 10 MBd Optocouplers Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Features The HCPL-261A family of optically coupled gates shown on this data sheet provide all the benefits of the industry standard 6N137 family with the added benefit of HCMOS compatible input current.
PAGE 2
Selection Guide Input Minimum CMR 8-Pin DIP (300 Mil) Small-Outline SO-8 (400 Mil) Widebody Hermetic dV/dt VCM (V/µs) (V) Single Channel Package NA NA On- Current Output (mA) Enable 5 5,000 50 10,000 1,000 Single Channel Package YES Dual Channel Package 6N137[1] NO YES NO NO 1,000 50 YES HCPL-2602[1] 3,500 300 YES HCPL-2612[1] 1,000 50 YES HCPL-261A 3 1,000 [2] 1,000 NO YES NO HCNW2601
PAGE 3
Ordering Information HCPL-xxxx is UL Recognized with 3750 Vrms for 1 minute per UL1577.
PAGE 4
HCPL-261A/261N/263A/263N Outline Drawing Pin Location (for reference only) 9.40 (0.370) 9.90 (0.390) TYPE NUMBER 8 7 6 5 OPTION CODE* A XXXXZ DATE CODE YYWW PIN ONE 1 2 3 0.20 (0.008) 0.33 (0.013) 6.10 (0.240) 6.60 (0.260) 7.36 (0.290) 7.88 (0.310) 5 TYP. 4 1.78 (0.070) MAX. 1.19 (0.047) MAX. DIMENSIONS IN MILLIMETERS AND (INCHES). 3.56 ± 0.13 (0.140 ± 0.005) 4.70 (0.185) MAX. 0.51 (0.020) MIN. 2.92 (0.115) MIN. 0.76 (0.030) 1.40 (0.056) * MARKING CODE LETTER FOR OPTION NUMBERS.
PAGE 5
HCPL-061A/061N/063A/063N Outline Drawing LAND PATTERN RECOMMENDATION 8 7 6 5 5.994 ± 0.203 (0.236 ± 0.008) XXX YWW 3.937 ± 0.127 (0.155 ± 0.005) TYPE NUMBER (LAST 3 DIGITS) 7.49 (0.295) DATE CODE 1 2 3 4 1.9 (0.075) 0.406 ± 0.076 (0.016 ± 0.003) 1.270 BSC (0.050) 0.64 (0.025) 7 * 5.080 ± 0.127 (0.200 ± 0.005) 3.175 ± 0.127 (0.125 ± 0.005) 0.432 (0.017) 45 X 0.228 ± 0.025 (0.009 ± 0.001) 1.524 (0.060) 0.203 ± 0.102 (0.008 ± 0.004) 0.305 MIN. (0.
PAGE 6
Insulation and Safety Related Specifications Parameter Symbol 8-Pin DIP (300 Mil) Value SO-8 Value Units Conditions Minimum External Air L(101) 7.1 4.9 mm Gap (External Clearance) Measured from input terminals to output terminals, shortest distance through air. Minimum External L(102) 7.4 4.8 mm Tracking (External Creepage) Measured from input terminals to output terminals, shortest distance path along body. Minimum Internal Plastic 0.08 0.
PAGE 7
Absolute Maximum Ratings Parameter Symbol Storage Temperature TS -55 125 °C Operating Temperature TA -40 +85 °C Max. Units Note Average Input Current IF(AVG) 10 mA Reverse Input Voltage VR 3 Volts Supply Voltage VCC -0.5 7 Volts Enable Input Voltage VE -0.5 5.
PAGE 8
Electrical Specifications Over recommended operating temperature (TA = - 40°C to +85°C) unless otherwise specified. Parameter Symbol Min. Typ.* Max. Units Test Conditions High Level Output Current IOH 3.1 100 µA Low Level Output VOL 0.4 0.6 V Voltage High Level Supply ICCH 7 10 mA Current 9 15 8 13 mA VCC = 5.5 V, IOL = 13 mA (sinking), IF = 3.0 mA, VE = 2.0 V VE = 0.
PAGE 9
Switching Specifications Over recommended operating temperature (TA = -40°C to +85°C) unless otherwise specified. Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note 7, 10 18 Propagation Delay tPLH 52 100 ns Time to High Output Level IF = 3.5 mA VCC = 5.
PAGE 10
Package Characteristics All Typicals at TA = 25°C Parameter Sym. Package* Min. Typ. Max. Units Test Conditions Fig. Note Input-Output VISO 3750 V rms Momentary With- OPT 020† 5000 stand Voltage** RH ≤ 50%, t = 1 min., TA = 25°C 5, 7 Input-Output Resistance Ω VI-O = 500 Vdc 4, 8 Input-Output CI-O 0.6 pF Capacitance f = 1 MHz, TA = 25°C 4, 8 Input-Input II-I Dual Channel 0.
PAGE 11
VCC = 5.5 V VO = 5.5 V VE = 2 V VF = 0.8 V 10 5 0 -60 -40 -20 0 20 40 60 80 100 TA – TEMPERATURE – C VOL – LOW LEVEL OUTPUT VOLTAGE – V VO – OUTPUT VOLTAGE – V RL = 350 Ω RL = 1 kΩ RL = 4 kW 1.0 0 0.5 1.0 1.5 40 20 0 -60 -40 -20 2.0 80 100 TA = 40 C TA = 25 C 0.1 0.01 1.0 1.1 1.2 IF + VF – 1.3 1.4 1.5 VF – FORWARD VOLTAGE – V Figure 6. Typical diode input forward current characteristic. HCPL-261A fig 6 VCC = 5.5 V VE = 2 V IF = 3.0 mA 0.5 IO = 16 mA IO = 12.8 mA 0.4 0.
PAGE 12
1.0 0.5 RL = 350 Ω RL = 1 kΩ RL = 4 kΩ VCC = 5 V VO = 0.6 V 0 -60 -40 -20 0 20 40 60 80 100 20 30 20 RL = 1 kΩ RL = 350 Ω 0 -60 -40 -20 0 20 40 60 80 100 TA – TEMPERATURE – C Figure 13. Typical pulse width distortion vs. temperature. HCPL-261A fig 13 TPLH RL = 350 kΩ 0 VCC = 5 V IF = 3.5 mA 20 40 60 80 100 HCPL-261A fig 11 tr, tf – RISE, FALL TIME – ns VCC = 5 V IF = 3.5 mA 40 TPHL RL = 350 Ω, 1 kΩ, 4 kΩ 40 160 RL = 4 kΩ 50 TPLH RL = 1 kΩ Figure 11.
PAGE 13
PULSE GEN. Z O = 50 Ω t f = t r = 5 ns INPUT VE MONITORING NODE HCPL-261A/261N VCC 8 2 7 3 6 0.1 µF BYPASS RL OUTPUT VO MONITORING NODE *C L 4 5 GND *CL IS APPROXIMATELY 15 pF WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE. 3.0 V INPUT VE 1.5 V t EHL t ELH OUTPUT VO 1.5 V tE – ENABLE PROPAGATION DELAY – ns 3.5 mA IF +5 V 1 120 90 VCC = 5 V VEH = 3 V VEL = 0 V IF = 3.
PAGE 14
Application Information SINGLE CHANNEL PRODUCTS GND BUS (BACK) Common-Mode Rejection for HCPL261A/HCPL-261N Families: VCC BUS (FRONT) Figure 20 shows the recommended drive circuit for the HCPL-261N/261A for optimal common-mode rejection performance. Two main points to note are: N.C. ENABLE (IF USED) 0.1µF OUTPUT 1 N.C. 1. The enable pin is tied to VCC rather than floating (this applies to single-channel parts only). N.C. ENABLE (IF USED) 0.1µF N.C. 2.
PAGE 15
CMR with Other Drive Circuits Table 1 indicates the directions of ILP and ILN flow depending on the direction of the common-mode transient. CMR performance with drive circuits other than that shown in Figure 20 may be enhanced by following these guidelines: For transients occurring when the LED is on, commonmode rejection (CMRL, since the output is in the “low” state) depends upon the amount of LED current drive (IF).
PAGE 16
VCC VCC HCPL-261X 820 Ω 1 HCPL-261A/261N 1N4148 2 74HC00 (OR ANY OPEN-COLLECTOR/ OPEN-DRAIN LOGIC GATE) LED 3 74HC04 (OR ANY TOTEM-POLE OUTPUT LOGIC GATE) 750 Ω HCPL-�261A fig 22 LED 4 Figure 24. CMOS gate drive circuit for HCPL-261A/-261N families. Table 1.
PAGE 17
The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure 26 shows that there will be uncertainty in both the data and the clock lines.