Datasheet

ManualsBrandsBROADCOM ManualsOptoelectronics & DisplaysGate-Drive-Optocoupler With High Integration Level DIP 8

Features

• 2.5 A maximum peak output current

• 2.0 A minimum peak output current

• 25 kV/µs minimum Common Mode Rejection (CMR) at

= 1500 V

• 0.5 V maximum low level output voltage (V

)

Eliminates need for negative gate drive

• I

= 5 mA maximum supply current

• Under Voltage Lock-Out protection (UVLO) with

hysteresis

• Wide operating V

range: 15 to 30 Volts

• 500 ns maximum switching speeds

• Industrial temperature range: -40°C to 100°C

• SafetyApproval:

UL Recognized

3750 Vrms for 1 min. for HCPL-3120/J312

5000 Vrms for 1 min. for HCNW3120

CSA Approval

IEC/EN/DIN EN 60747-5-2 Approved

IORM

= 630 V

peak

for HCPL-3120 (Option 060)

IORM

= 891 V

peak

for HCPL-J312

IORM

= 1414 V

peak

for HCNW3120

Applications

• IGBT/MOSFET gate drive

• AC/Brushless DC motor drives

• Industrial inverters

• Switch mode power supplies

HCPL-3120/J312, HCNW3120

2.5 Amp Output Current IGBT Gate Drive Optocoupler

Data Sheet

Lead (Pb) Free

RoHS 6 fully

compliant

RoHS 6 fully compliant options available;

-xxxE denotes a lead-free product

CAUTION: It is advised that normal static precautions be taken in handling and assembly

of this component to prevent damage and/or degradation which may be induced by ESD.

Description

The HCPL-3120 contains a GaAsP LED while the HCPL-

J312 and the HCNW3120 contain an AlGaAs LED. The LED

is optically coupled to an integrated circuit with a power

output stage. These optocouplers are ideally suited for

driving power IGBTs and MOSFETs used in motor control

inverter applications. The high operating voltage range

of the output stage provides the drive voltages required

by gate controlled devices. The voltage and current

supplied by these optocouplers make them ideally

suited for directly driving IGBTs with ratings up to 1200

V/100 A. For IGBTs with higher ratings, the HCPL-3120

series can be used to drive a discrete power stage which

drives the IGBT gate. The HCNW3120 has the highest in-

sulation voltage of V

IORM

= 1414 Vpeak in the IEC/EN/DIN

EN 60747-5-2. The HCPL-J312 has an insulation voltage

of V

IORM

= 891 V

peak

and the V

IORM

= 630 V

peak

is also

available with the HCPL-3120 (Option 060).

A 0.1 µF bypass capacitor must be connected between pins 5 and 8.

TRUTH TABLE

LED

- V

“POSITIVE GOING”

(i.e., TURN-ON)

- V

“NEGATIVE GOING”

(i.e., TURN-OFF) V

OFF 0 - 30 V 0 - 30 V LOW

ON 0 - 11 V 0 - 9.5 V LOW

ON 11 - 13.5 V 9.5 - 12 V TRANSITION

ON 13.5 - 30 V 12 - 30 V HIGH

Functional Diagram

SHIELD

N/C

CATHODE

ANODE

N/C

SHIELD

N/C

CATHODE

ANODE

N/C

HCNW3120

HCPL-3120/J312

Summary of content (24 pages)

PAGE 1
HCPL-3120/J312, HCNW3120 2.5 Amp Output Current IGBT Gate Drive Optocoupler Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Features The HCPL-3120 contains a GaAsP LED while the HCPLJ312 and the HCNW3120 contain an AlGaAs LED. The LED is optically coupled to an integrated circuit with a power output stage.
PAGE 2
Selection Guide Part Number HCPL-3120 HCPL-J312 HCNW3120 HCPL-3150* Output Peak Current ( IO) 2.5 A 2.5 A 2.5 A 0.6 A IEC/EN/DIN EN 60747-5-2 Approval VIORM = 630 Vpeak VIORM = 891 Vpeak VIORM = 1414 Vpeak (Option 060) VIORM = 630 Vpeak (Option 060) *The HCPL-3150 Data sheet available. Contact Avago sales representative or authorized distributor. Ordering Information HCPL-3120 and HCPL-J312 are UL recognized with 3750 Vrms for 1 minute per UL1577.
PAGE 3
Package Outline Drawings HCPL-3120 Outline Drawing (Standard DIP Package) 7.62 ± 0.25 (0.300 ± 0.010) 9.65 ± 0.25 (0.380 ± 0.010) 8 TYPE NUMBER 7 6 5 6.35 ± 0.25 (0.250 ± 0.010) OPTION CODE* DATE CODE A XXXXZ YYWW 1 2 3 4 1.78 (0.070) MAX. 1.19 (0.047) MAX. + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002) 5° TYP. 3.56 ± 0.13 (0.140 ± 0.005) 4.70 (0.185) MAX. 0.51 (0.020) MIN. 2.92 (0.115) MIN. DIMENSIONS IN MILLIMETERS AND (INCHES). 1.080 ± 0.320 (0.043 ± 0.
PAGE 4
Package Outline Drawings HCPL-J312 Outline Drawing (Standard DIP Package) 7.62 ± 0.25 (0.300 ± 0.010) 9.80 ± 0.25 (0.386 ± 0.010) 8 TYPE NUMBER 7 6 5 6.35 ± 0.25 (0.250 ± 0.010) DATE CODE A XXXX YYWW 1 2 3 4 1.78 (0.070) MAX. 1.19 (0.047) MAX. 5° TYP. 3.56 ± 0.13 (0.140 ± 0.005) + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002) 4.70 (0.185) MAX. 0.51 (0.020) MIN. 2.92 (0.115) MIN. 1.080 ± 0.320 (0.043 ± 0.013) DIMENSIONS IN MILLIMETERS AND (INCHES). OPTION NUMBERS 300 AND 500 NOT MARKED. 0.
PAGE 5
HCNW3120 Outline Drawing (8-Pin Wide Body Package) 11.00 MAX. (0.433) 11.15 ± 0.15 (0.442 ± 0.006) 8 7 6 9.00 ± 0.15 (0.354 ± 0.006) 5 TYPE NUMBER A HCNWXXXX DATE CODE YYWW 1 2 3 4 10.16 (0.400) TYP. 1.55 (0.061) MAX. 7° TYP. + 0.076 0.254 - 0.0051 + 0.003) (0.010 - 0.002) 5.10 MAX. (0.201) 3.10 (0.122) 3.90 (0.154) 0.51 (0.021) MIN. 2.54 (0.100) TYP. 1.78 ± 0.15 (0.070 ± 0.006) 0.40 (0.016) 0.56 (0.022) DIMENSIONS IN MILLIMETERS (INCHES). NOTE: FLOATING LEAD PROTRUSION IS 0.
PAGE 6
Solder Reflow Temperature Profile 300 PREHEATING RATE 3 °C + 1 °C/–0.5 °C/SEC. REFLOW HEATING RATE 2.5 °C ± 0.5 °C/SEC. 200 PEAK TEMP. 245 °C PEAK TEMP. 240 °C TEMPERATURE (°C) 2.5 C ± 0.5 °C/SEC. 30 SEC. 160 °C 150 °C 140 °C PEAK TEMP. 230 °C SOLDERING TIME 200 °C 30 SEC. 3 °C + 1 °C/–0.5 °C 100 PREHEATING TIME 150 °C, 90 + 30 SEC. 50 SEC. TIGHT TYPICAL LOOSE ROOM TEMPERATURE 0 0 50 100 150 TIME (SECONDS) NOTE: NON-HALIDE FLUX SHOULD BE USED.
PAGE 7
Regulatory Information Agency/Standard HCPL-3120 HCPL-J312 HCNW3120 Underwriters Laboratory (UL) Recognized under UL 1577, Component Recognition Program, Category, File E55361 Compliant Compliant Compliant Canadian Standards Association (CSA) File CA88324, per Component Acceptance Notice #5 Compliant Compliant Compliant IEC/EN/DIN EN 60747-5-2 Compliant Option 060 Compliant Compliant Insulation and Safety Related Specifications Parameter Symbol HCPL3120 Value HCPLJ312 HCNW 3120
PAGE 8
All Avago data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board, minimum creep-age and clearance requirements must be met as specified for individual equipment standards.
PAGE 9
Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature TS -55 125 °C Operating Temperature TA -40 100 °C Average Input Current IF(AVG) 25 mA Peak Transient Input Current (<1 µs pulse width, 300 pps) IF(TRAN) 1.0 A Reverse Input Voltage VR 5 Volts HCPL-J312 HCNW3120 5 HCPL-3120 Note 1 “High” Peak Output Current IOH(PEAK) 2.5 A 2 “Low” Peak Output Current IOL(PEAK) 2.
PAGE 10
Electrical Specifications (DC) Over recommended operating conditions (TA = -40 to 100°C, for HCPL-3120, HCPL-J312 IF(ON) = 7 to 16mA, for HCNW3120 IF(ON) = 10 to 16mA, VF(OFF) = -3.6 to 0.8 V, VCC = 15 to 30 V, VEE = Ground) unless otherwise specified. Parameter Symbol Device Min. Typ.* Max. High Level Output IOH Current 0.5 1.5 Units Test Conditions Fig. Note A VO = (VCC - 4 V) 2, 3, 5 2 2.0 A VO = (VCC - 15 V) 17 0.5 A VO = (VEE + 2.
PAGE 11
Switching Specifications (AC) Over recommended operating conditions (TA = -40 to 100°C, for HCPL-3120,HCPL-J312 IF(ON) = 7 to 16mA, for HCNW3120 IF(ON) = 10 to 16mA, VF(OFF) = -3.6 to 0.8 V, VCC = 15 to 30 V, VEE = Ground) unless otherwise specified. Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note Propagation Delay Time tPLH 0.10 0.30 0.50 µs to High Output Level Rg = 10 Ω, Cg = 10 nF, 10, 11, 16 12, 13, Propagation Delay Time tPHL 0.10 0.30 0.
PAGE 12
Package Characteristics Over recommended temperature (TA = -40 to 100°C) unless otherwise specified. Parameter Symbol Device Min. Input-Output Momentary VISO HCPL-3120 3750 Withstand Voltage** HCPL-J312 HCNW3120 Typ. Max. Units Test Conditions 8, 11 3750 t = 1 min., 9, 11 5000 TA = 25°C 10, 11 1012 VI-O = 500 VDC 11 HCPL-3120 HCPL-J312 HCNW3120 Ω 1012 1013 TA = 25°C 1011 TA = 100°C HCPL-3120 0.
PAGE 13
-3 -4 -40 -20 0 20 40 60 80 100 1.8 1.6 1.4 1.2 1.0 -40 -20 TA – TEMPERATURE – °C IOL – OUTPUT LOW CURRENT – A VOL – OUTPUT LOW VOLTAGE – V 80 100 0.20 0.15 0.10 0.05 -20 0 20 40 60 80 100 3 2 1 0 -40 -20 0 20 40 60 80 100 ICC – SUPPLY CURRENT – mA 3.0 2.5 VCC = 30 V VEE = 0 V IF = 10 mA for ICCH IF = 0 mA for ICCL 80 TA – TEMPERATURE – °C Figure 7. ICC vs. temperature. HCPL-3120 fig 7 0 0.5 100 ICCH ICCL 3.0 2.
PAGE 14
4 3 2 1 0 -40 -20 0 20 40 60 80 100 TA – TEMPERATURE – °C HCPL-J312 5 VCC = 15 TO 30 V VEE = 0 V OUTPUT = OPEN 4 3 2 1 0 -40 -20 0 20 40 60 80 100 TA – TEMPERATURE – °C IFLH – LOW TO HIGH CURRENT THRESHOLD – mA VCC = 15 TO 30 V VEE = 0 V OUTPUT = OPEN IFLH – LOW TO HIGH CURRENT THRESHOLD – mA IFLH – LOW TO HIGH CURRENT THRESHOLD – mA HCPL-3120 5 HCNW3120 5 VCC = 15 TO 30 V VEE = 0 V OUTPUT = OPEN 4 3 2 1 0 -40 -20 0 20 40 60 80 100 TA – TEMPERATURE – °C Figure 9.
PAGE 15
30 VO – OUTPUT VOLTAGE – V VO – OUTPUT VOLTAGE – V 25 20 15 10 5 0 HCPL-J312 35 0 1 2 3 4 30 25 20 15 10 5 0 5 IF – FORWARD LED CURRENT – mA 0 1 2 3 4 5 IF – FORWARD LED CURRENT – mA Figure 15. Transfer characteristics. HCPL-3120 fig 15 HCPL-3120 1000 100 IF + 10 VF – 1.0 0.1 0.01 0.001 1.10 1.20 1.30 1.40 1.50 HCPL-J312/HCNW3120 1000 TA = 25°C IF – FORWARD CURRENT – mA IF – FORWARD CURRENT – mA HCPL-3120 fig 15b TA = 25°C 100 IF + VF – 10 1.0 0.1 0.01 0.001 1.2 1.
PAGE 16
1 8 2 7 0.1 µF 3 6 1 8 2 7 0.1 µF IOL + VCC = 15 – to 30 V 2.5 V + – VOH IF = 7 to 16 mA + VCC = 15 – to 30 V 3 6 100 mA 4 5 4 Figure 18. IOL Test circuit. Figure 19. VOH Test circuit. HCPL-3120 fig 18 1 HCPL-3120 fig 19 8 0.1 µF 2 1 3 6 4 5 8 0.1 µF 100 mA 7 2 + VCC = 15 – to 30 V 7 IF VOL Figure 20. VOL Test circuit. 3 6 4 5 Figure 21. IFLH Test circuit. HCPL-3120 fig 20 HCPL-3120 fig 21 1 8 0.1 µF 2 7 IF = 10 mA 3 6 4 5 Figure 22. UVLO test circuit.
PAGE 17
1 8 0.1 µF IF = 7 to 16 mA + 10 KHz – 500 Ω 50% DUTY CYCLE 2 + – 7 IF VCC = 15 to 30 V tr tf VO 3 6 90% 10 Ω 50% VOUT 10 nF 4 10% 5 tPLH tPHL Figure 23. tPLH, tPHL, tr, and tf test circuit and waveforms. HCPL-3120 fig 23 VCM IF 5V + – 1 δt 0.1 µF A B δV 8 2 VO 6 4 5 VCC = 30 V VO VOH SWITCH AT A: IF = 10 mA – SWITCH AT B: IF = 0 mA VCM = 1500 V Figure 24. CMR test circuit and waveforms.
PAGE 18
Applications Information Eliminating Negative IGBT Gate Drive (Discussion applies to HCPL-3120, HCPL-J312, and HCNW3120) To keep the IGBT firmly off, the HCPL-3120 has a very low maximum VOL specification of 0.5 V. The HCPL-3120 realizes this very low VOL by using a DMOS transistor with 1 Ω (typical) on resistance in its pull down circuit. When the HCPL-3120 is in the low state, the IGBT gate is shorted to the emitter by Rg + 1 Ω.
PAGE 19
Selecting the Gate Resistor (Rg) to Minimize IGBT Switching Losses. (Discussion applies to HCPL-3120, HCPL-J312 and HCNW3120) For the circuit in Figure 26 with IF (worst case) = 16 mA, Rg = 8 Ω, Max Duty Cycle = 80%, Qg = 500 nC, f = 20 kHz and TA max = 85 °C: Step 1: Calculate Rg Minimum from the IOL Peak Specifica tion. The IGBT and Rg in Figure 26 can be analyzed as a simple RC circuit with a voltage supplied by the HCPL3120.
PAGE 20
Thermal Model (Discussion applies to HCPL-3120, HCPLJ312 and HCNW3120) The steady state thermal model for the HCPL-3120 is shown in Figure 28. The thermal resistance values given in this model can be used to calculate the temperatures at each node for a given operating condition. As shown by the model, all heat generated flows through qCA which raises the case temperature TC accordingly. The value of qCA depends on the conditions of the board design and is, therefore, determined by the designer.
PAGE 21
θLD = 442 °C/W TJE TJD θLC = 467 °C/W θDC = 126 °C/W TC θCA = 83 °C/W* TA TJE = LED junction temperature TJD T=JEdetector IC junction temperature = LED JUNCTION TEMPERATURE = DETECTOR IC JUNCTION TEMPERATURE TC TT=JD=case temperature measured at the center of the package bottom C CASE TEMPERATURE MEASURED AT THE qLC = LED-to-case thermal resistance CENTER OF THE PACKAGE BOTTOM = LED-TO-CASE THERMAL RESISTANCE qLD θ=LCLED-to-detector thermal resistance θLD = LED-TO-DETECTOR THERMAL RESISTANCE qDC θ=DCde
PAGE 22
CMR with the LED On (CMRH). A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by overdriving the LED current beyond the input threshold so that it is not pulled below the threshold during a transient. A minimum LED current of 10 mA provides adequate margin over the maximum IFLH of 5 mA to achieve 25 kV/ µs CMR. RSAT and VSAT of the logic gate.
PAGE 23
Under Voltage Lockout Feature. (Discussion applies to HCPL-3120, HCPL-J312, and HCNW3120) The HCPL-3120 contains an under voltage lockout (UVLO) feature that is designed to protect the IGBT under fault conditions which cause the HCPL-3120 supply voltage (equivalent to the fully-charged IGBT gate voltage) to drop below a level necessary to keep the IGBT in a low resistance state. When the HCPL-3120 output is in the high state and the supply voltage drops below the HCPL3120 VUVLO– threshold (9.
PAGE 24
To minimize dead time in a given design, the turn on of LED2 should be delayed (relative to the turn off of LED1) so that under worst-case con-ditions, transistor Q1 has just turned off when transistor Q2 turns on, as shown in Figure 35. The amount of delay necessary to achieve this conditions is equal to the maximum value of the propagation delay difference specification, PDDMAX, which is specified to be 350 ns over the operating temperature range of ‑40°C to 100°C.